From IDDQ Fault Detection to Defect Localization in Logic CMOS Integrated Circuits: Key Issues

1999 ◽  
Author(s):  
Philippe Perdu ◽  
Romain Desplats
Keyword(s):  
Fault Detection ◽  
Integrated Circuits ◽  
Test Pattern ◽  
Pattern Generation ◽  
Fault Isolation ◽  
Iddq Testing ◽  
Accurate Localization ◽  
Contactless Testing ◽  
Defect Localization ◽  
Key Issues

Abstract IDDQ testing detects a majority of faults in logic ICs. To improve defect coverage with very short test patterns, IDDQ testing has been integrated in fault simulators embedded with automatic test pattern generation (ATPG) algorithms. Nevertheless, for failure analysis purposes, this progress has not eliminated the complex task of fault isolation at the silicon level of ICs. Defect localization is facilitated with IDDQ testing because the defect is detected as soon as it is activated inside the device. At the failed vector, abnormal IDDQ current is measured and accurate localization of the corresponding defect inside the chip can be performed. Thermally related techniques or emission microscopy can be used for this localization process. Very powerful tools like electron beam testers can also be used to deeply analyze faulty devices by internal contactless testing. In this paper, we will present an application of IDDQ testing for fault detection and some key issues regarding localization of the corresponding defect: • Appropriate techniques, • Switching from electrical testing to fault localization, • Modifying the test pattern to shorten the localization process, • Constructing a localization method based on an IDDQ diagnostic.

Faster Defect Localization with a New Development of IDDQ

1998 ◽  
Author(s):  
Romain Desplats ◽  
Philippe Perdu ◽  
Jamel Benbrik ◽  
Michel Dupire
Keyword(s):  
Test Pattern ◽  
Pattern Generation ◽  
Equipotential Line ◽  
Test Pattern Generation ◽  
Automatic Test Pattern Generation ◽  
Iddq Testing ◽  
New Development ◽  
Defect Localization ◽  
Extended Range ◽  
Voltage Contrast

Abstract Recent progress with IDDQ testing has demonstrated the ability to identify a majority of defects in logic ICs. IDDQ testing has also been integrated in fault simulators embedded with automatic test pattern generation (ATPG) algorithms to further extend defect coverage. However, this progress has not eliminated the complex task of defect localization on the silicon level of ICs. To deal with the challenge of faster and more accurate defect localization with greater sensitivity, we have developed a new method based on voltage contrast capabilities for internal localization of IDDQ defects. This method covers an extended range of cases: functional or non functional devices, with or without CAD information, etc... Using only the same test pattern as that used to identify a faulty circuit, the equipotential line of the failure can be located. This approach can also be extended to coupling with netlist information. For example, the equipotential line previously found on the faulty circuit can be compared with the fault simulator output. Then, the site of the simulated defect corresponding to the physical failure can be extracted and local deprocessing with a FIB can be used on the failed circuit to physically reveal the defect with an improved turn around time.

Fault Isolation of Open Defects Using Space Domain Reflectometry

2012 ◽  
Author(s):  
Mayue Xie ◽  
Zhiguo Qian ◽  
Mario Pacheco ◽  
Zhiyong Wang ◽  
Rajen Dias ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Fault Isolation ◽  
Nondestructive Technique ◽  
Space Domain ◽  
New Approach ◽  
Defect Localization ◽  
Open Faults ◽  
Open Defects ◽  
Application Optimization ◽  
Rf Magnetic Field

Abstract Recently, a new approach for isolation of open faults in integrated circuits (ICs) was developed. It is based on mapping the radio-frequency (RF) magnetic field produced by the defective part fed with RF probing current, giving the name to Space Domain Reflectometry (SDR). SDR is a non-contact and nondestructive technique to localize open defects in package substrates, interconnections and semiconductor devices. It provides 2D failure isolation capability with defect localization resolution down to 50 microns. It is also capable of scanning long traces in Si. This paper describes the principles of the SDR and its application for the localization of open and high resistance defects. It then discusses some analysis methods for application optimization, and gives examples of test samples as well as case studies from actual failures.

Improving Fault Isolation Using Iterative Diagnosis

2008 ◽  
Author(s):  
Kevin Gearhardt ◽  
Chris Schuermyer ◽  
Ruifeng Guo
Keyword(s):  
Fault Diagnosis ◽  
Failure Analysis ◽  
Test Generation ◽  
Pattern Generation ◽  
Fault Isolation ◽  
Isolation Techniques ◽  
Defect Localization

Abstract This paper presents an iterative diagnosis test generation framework to improve logic fault diagnosis resolution. Industrial examples are presented in this paper on how additional targeted pattern generation can be used to improve defect localization before physical failure analysis of a die. This enables failure analysts to be more effective by reducing the dependence on the more expensive physical fault isolation techniques.

Backside Deprocessing of CMOS SOI Devices for Physical Defect and Failure Analysis

2003 ◽  
Author(s):  
Seth J. Prejean ◽  
Joseph Shannon
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Flip Chip ◽  
Fault Isolation ◽  
Oxide Semiconductor ◽  
Easy Access ◽  
Induced Voltage ◽  
Emission Analysis ◽  
Defect Localization ◽  
Soi Devices

Abstract This paper describes improvements in backside deprocessing of CMOS (Complimentary Metal Oxide Semiconductor) SOI (Silicon On Insulator) integrated circuits. The deprocessing techniques described here have been adapted from a previous research publication on backside deprocessing of bulk CMOS integrated circuits [1]. The focus of these improvements was to provide a repeatable and reliable methodology of deprocessing CMOS devices from the backside. We describe a repeatable and efficient technique to deprocess flip chip packaged devices and unpackaged die from the backside. While this technique has been demonstrated on SOI and bulk devices, this paper will focus on the latest SOI technology. The technique is useful for quick and easy access to the transistor level while preserving the metal interconnects for further analysis. It is also useful for deprocessing already thinned or polished die without removing them from the package. Removing a thin die from a package is very difficult and could potentially damage the device. This is especially beneficial when performing physical failure analysis of samples that have been back thinned for the purpose of fault isolation and defect localization techniques such as: LIVA (Laser Induced Voltage Alteration), TIVA (Thermally Induce Voltage Alteration), SDL [2] (Soft Defect Localization), and TRE (Time Resolved Emission) analysis. An important fundamental advantage of deprocessing SOI devices is that the BOX (Buried Oxide) layer acts as a chemical etch stop when etching the backside or bulk silicon. This leaves the transistor active silicon intact for analysis. Further delayering allows for the inspection of the active silicon, gate oxide, silicide, spacers, and poly. After deprocessing the transistor level, the metal layers are still intact and, in most cases, still electrically connected to the outside world. This can provide additional failure analysis opportunities.

Zynq SOC Low-Voltage and Temperature-Dependent L2 Cache Failure Diagnosis and Defect Localization Case Study

2017 ◽  
Author(s):  
Haonan Bai ◽  
Lan Yin Lee ◽  
Yang Jing ◽  
Peter Floyd Salinas ◽  
Kok Keng Chua
Keyword(s):  
Failure Analysis ◽  
Low Voltage ◽  
Data Access ◽  
Pattern Generation ◽  
Fault Isolation ◽  
Programmable Logic ◽  
Single Chip ◽  
Tem Analysis ◽  
Test Methodology ◽  
Defect Localization

Abstract Failure analysis and defect localization on 28nm All Programmable Zynq System-on-Chip (SoC) device is extremely challenging. While conventional FPGA, which only consists of the Programmable Logic, has greater ease and flexibility in pattern generation during fault isolation, the all programmable SoC device integrates a dual ARM Cortex-A9 cores with Programmable Logic (PL) in a single chip. The cache data access in-between processor and PL is more complex and test methodology has lesser degree of control on cache data flow and stack sequence. This paper introduced an advanced fault isolation test methodology combining Software Development Kit (SDK) with scan based diagnostic test for cache failures. It successfully pinpoint to failure locations with physical defects found. As conventional physical failure analysis approaches using SEM based passive voltage contrast could not observe any abnormalities, current imaging and nano-probing measurement using AFP played critical roles in detecting nano-ampere leakages prior subsequent TEM analysis. The findings were then feedback to the foundry for process improvement. Furthermore, a new screening methodology is innovated where an extreme low-voltage test at high temperature in Automatic Test to detect and eliminate the process marginal leakage failure.

Application of PEM and OBIRCH to Defect Localization of Integrated Circuits

2014 ◽  
Vol 904 ◽  
pp. 277-281
Author(s):  
Jian Wen Lian ◽  
Xiao Ling Lin ◽  
Ruo He Yao
Keyword(s):  
Integrated Circuits ◽  
Failure Mechanisms ◽  
Photon Emission ◽  
Fault Isolation ◽  
Resistance Change ◽  
Microelectronic Devices ◽  
Application Condition ◽  
Defect Localization ◽  
Metal Interconnects ◽  
Fault Characterization

With the increasing integration and complexity of microelectronic devices, fault isolation has been challenged. Photon Emission Microscopy (PEM) and Optical Beam Induced Resistance Change (OBIRCH) are effective tools for defect localization and fault characterization in failure analysis. In this paper, the principles and different application condition of PEM and OBIRCH are discussed. PEM is very helpful for locating defects emitting photon, but can not detect the defects which have no photon emitting, such as shorted metal interconnects; OBIRCH as a complementary, has a high success rate for locating resistance defects. Two cases with failure mechanisms illuminated are presented to show the different application of PEM and OBIRCH.

scholarly journals Soft Computing Approach To Automatic Test Pattern Generation For Sequential Vlsi Circuit

2013 ◽  
pp. 42-47
Author(s):  
Monalisa Mohanty ◽  
S. N. Patnaik
Keyword(s):  
Integrated Circuits ◽  
Test Pattern ◽  
Difficult Problem ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Test Sequence ◽  
Test Pattern Generation ◽  
Automatic Test Pattern Generation ◽  
Automatic Test ◽  
Sequence Generation

Due to the constant development in the integrated circuits, the automatic test pattern generation problem become more vital for sequential vlsi circuits in these days. Also testing of integrating circuits and systems has become a difficult problem. In this paper we have discussed the problem of the automatic test sequence generation using particle swarm optimization(PSO) and technique for structure optimization of a deterministic test pattern generator using genetic algorithm(GA).

Transition Test Patterns Generation for BIST Implemented in ASIC and FPGA

2008 ◽  
Vol 144 ◽  
pp. 214-219
Author(s):  
Vidas Abraitis ◽  
Žydrūnas Tamoševičius
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Test Pattern ◽  
Pattern Generation ◽  
Linear Feedback ◽  
Test Sequence ◽  
Self Testing ◽  
Field Programmable ◽  
Application Specific Integrated Circuit ◽  
Transition Delay

Transition delay testing of sequential circuits in a clocked environment is analyzed. There are presented two test pattern generator methods for built in self testing of the circuit implemented as Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) of Virtex family. Cellular automaton and Linear Feedback Shift Register (LFSR) structures are used for test sequence generation. The circuits are tested as the black boxes under Transition fault model. Experimental results of the test pattern generation methods are presented and analyzed. Results compared with exhaustive test of transition faults for ASICs and programmable integrated circuits with given configuration.

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