UV-Raman Microscopy on the Analysis of Ultra-Low-k Dielectric Materials on Patterned Wafers

2013 ◽  
Author(s):  
Maggie Y.M. Huang ◽  
Tsu Hau Ng ◽  
Hao Tan ◽  
Mohammed Khalid Bin Dawood ◽  
Pik Kee Tan ◽  
...  
Keyword(s):  
Silicon Oxide ◽  
Dielectric Breakdown ◽  
Process Integration ◽  
Dielectric Materials ◽  
Raman Microscopy ◽  
Three Dimension ◽  
Cu Metallization ◽  
Patterned Wafers ◽  
Uv Raman ◽  
Low K

Abstract With the shrinkage of the IC device dimensions, Cu and ultra-low-k dielectric were introduced into IC devices to reduce RC delay. Ultra-low-k dielectrics generally suffer more damage than silicon oxide dielectric during process integration and subsequently cause reliability degradation. Therefore, ultra-low-k damage characterization on Cu damascene structures is of great importance to understand the damage mechanisms. This paper describes the application of UV-Raman microscopy with enhanced spatial resolution and signal sensitivity for characterizing ultra-low-k dielectric in the three-dimension structure of Cu metallization with nanometer feature size. It shows UV-Raman technique has an advantage in analyzing ultra-low-k layer on patterned wafer and extracting ultra-low-k signals from Cu/ultra-low-k mixed structure. UV-Raman is also effective to characterize the ultra-low-k degradation for ultra-low-k related reliability analysis by time dependent dielectric breakdown (TDDB) test.

UV-Raman Microscopy on the Analysis of Ultra-Low-K Dielectric Materials on Patterned Wafers

2013 ◽  
Vol 740 ◽  
pp. 680-689 ◽  
Author(s):  
Maggie Y.M. Huang ◽  
Jeffrey C.K. Lam ◽  
Hao Tan ◽  
Tsu Hau Ng ◽  
Mohammed Khalid Bin Dawood ◽  
...  
Keyword(s):  
Silicon Oxide ◽  
Dielectric Breakdown ◽  
Process Integration ◽  
Dielectric Materials ◽  
Raman Microscopy ◽  
Three Dimension ◽  
Cu Metallization ◽  
Patterned Wafers ◽  
Uv Raman ◽  
Low K

With the shrinkage of the IC device dimension, Cu and ultra-low-k dielectric were introduced into IC devices to reduce the RC delay. Ultra-low-k dielectrics generally suffer more damage than silicon oxide dielectric during process integration and subsequently cause reliability degradation. Therefore, ultra-low-k damage characterization on Cu damascene structures is of great importance to understand the damage mechanisms. This paper describes the application of UV-Raman microscopy with enhanced spatial resolution and signal sensitivity for characterizing ultra-low-k dielectric in the three-dimension structure of Cu metallization with nanometer feature size. It shows UV-Raman technique has an advantage in analyzing ultra-low-k layer on patterned wafer and extracting ultra-low-k signals from Cu/ultra-low-k mixed structure. UV-Raman is also effective to characterize the ultra-low-k degradation for ultra-low-k related reliability analysis by time dependent dielectric breakdown (TDDB) test.

Methods And Needs For Low K Material Research

1995 ◽  
Vol 381 ◽  
Author(s):  
Chiu H. Ting ◽  
Thomas E. Seidel
Keyword(s):  
High Performance ◽  
Process Integration ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Material Research ◽  
Material Development ◽  
Device Reliability ◽  
New Material ◽  
Speed Up ◽  
Low K

AbstractFor several years the industry has recognized the need of developing low k dielectric material and high conductivity metal for high performance interconnect. Low k dielectric will impact both power and delay favorably, while higher conductivity metal will reduce delay time. In order to be useful, new low k dielectric materials must be carefully characterized for their electrical, chemical, thermal and mechanical properties. In addition, their impact on process integration, fabrication cost and device reliability must also be considered. Since the gestation period for introducing a new material is very long, a set of standard testing methodologies are required to speed up the development process. This review will discuss various material options and the progress of material development and characterization methodologies. Example results will be provided for assessing these parameters.

Overview Of Process Integration Issues For Low K Dielectrics

1998 ◽  
Vol 511 ◽  
Author(s):  
R. H. Havemann ◽  
M. K. Jain ◽  
R. S. List ◽  
A. R. Ralston ◽  
W-Y. Shih ◽  
...  
Keyword(s):  
Large Scale ◽  
Process Integration ◽  
Functional Integration ◽  
Dielectric Materials ◽  
Limiting Factor ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
Rc Delay ◽  
Low K

ABSTRACTThe era of silicon Ultra-Large-Scale-Integration (ULSI) has spurred an everincreasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. Both interconnect resistance and capacitance play key roles in overall performance, but modeling simulations have highlighted the importance of reducing parasitic capacitance to manage crosstalk, power dissipation and RC delay. New dielectric materials with lower permittivity (k) are needed to meet this challenge. This paper summarizes the process integration and reliability issues associated with the use of novel low k materials in multilevel interconnects.

Process Integration issues for Interlevel Dielectric Materials for Sub-quarter Micron Silicon Integrated Circuits

1998 ◽  
Vol 511 ◽  
Author(s):  
Vijay Parihar ◽  
R. Singh
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Process Integration ◽  
Dielectric Materials ◽  
New Approach ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Silicon Integrated Circuits ◽  
Processing Techniques ◽  
Low K

ABSTRACTThe continued miniaturization towards sub-quarter micron feature size mandates the search for low dielectric constant interlayer dielectric materials. A large number of materials and processing techniques has been suggested, but so far none of the proposed dielectric materials as well as processing techniques have been integrated into standard integrated circuit processing. In this paper, a new approach has been formulated for integration of low-k dielectric materials for future integrated circuits.

Integration Issues for Low Dielectric Constant Materials in each Generation of ULSI'S

1999 ◽  
Vol 565 ◽  
Author(s):  
Hideki Gomi ◽  
Koji Kishimoto ◽  
Tatsuya Usami ◽  
Ken-ichi Koyanagi ◽  
Takashi Yokoyama ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Silicon Oxide ◽  
Process Integration ◽  
Low Dielectric Constant ◽  
Next Generation ◽  
Hydrogen Silsesquioxane ◽  
Low Dielectric ◽  
Low Dielectric Constant Materials ◽  
Fluorinated Silicon Oxide ◽  
Low K

AbstractThe technologies utilizing Fluorinated Silicon Oxide (FSG, k=3.6) and Hydrogen Silsesquioxane (HSQ, k=3.0) have been established for 0.25-μm and 0.18-μm generation ULSIs. However, low-k materials for the next generation ULSIs, which have a dielectric constant of less than 3.0, have not become mature yet. In this paper, we review process integration issues in applying FSG and HSQ, and describe integration results and device performance using Fluorinated Amorphous Carbon (a-C:F, k=2.5) as one of the promising low-k materials for the next generation ULSIs.

Integration Issues for Low Dielectric Constant Materials in each Generation of ULSI's

1999 ◽  
Vol 564 ◽  
Author(s):  
Hideki Gomi ◽  
Koji Kishimoto ◽  
Tatsuya Usami ◽  
Ken-ichi Koyanagi ◽  
Takashi Yokoyama ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Silicon Oxide ◽  
Process Integration ◽  
Low Dielectric Constant ◽  
Next Generation ◽  
Hydrogen Silsesquioxane ◽  
Low Dielectric ◽  
Low Dielectric Constant Materials ◽  
Fluorinated Silicon Oxide ◽  
Low K

AbstractThe technologies utilizing Fluorinated Silicon Oxide (FSG, k=3.6) and Hydrogen Silsesquioxane (HSQ, k=3.0) have been established for 0.25-µm and 0.1 8-µm generation ULSIs. However, low-k materials for the next generation ULSIs, which have a dielectric constant of less than 3.0, have not become mature yet. In this paper, we review process integration issues in applying FSG and HSQ, and describe integration results and device performance using Fluorinated Amorphous Carbon (a-C:F, k=2.5) as one of the promising low-k materials for the next generation ULSIs.

Vibrational spectroscopy of low-k/ultra-low-k dielectric materials on patterned wafers

2011 ◽  
Vol 29 (5) ◽  
pp. 051513 ◽  
Author(s):  
Jeffrey C. K. Lam ◽  
Maggie Y. M. Huang ◽  
Hao Tan ◽  
Zhiqiang Mo ◽  
Zhihong Mai ◽  
...  
Keyword(s):  
Vibrational Spectroscopy ◽  
Dielectric Materials ◽  
Patterned Wafers ◽  
Low K

Structure-Property Correlation in Low K Dielectric Materials

1999 ◽  
Vol 565 ◽  
Author(s):  
Michael Morgen ◽  
Jie-Hua Zhao ◽  
Michael Hay ◽  
Taiheui Cho ◽  
Paul S. Ho
Keyword(s):  
Dielectric Constant ◽  
Mechanical Stability ◽  
Process Integration ◽  
Dielectric Materials ◽  
Thermomechanical Properties ◽  
Low Dielectric Constant ◽  
Structure Property ◽  
Material Development ◽  
Low Dielectric ◽  
Low K

AbstractIn recent years there have been widespread efforts to identify low dielectric constant materials that can satisfy a number of diverse performance requirements necessary for successful integration into IC devices. This has led to extensive efforts to develop low k materials and the associated process integration. A particularly difficult challenge for material development has been to find the combination of low dielectric constant and good thermal and mechanical stability. In this paper recent characterization results for low k materials performed at the University of Texas will be reviewed, with an emphasis on the relationship of chemical structure to the aforementioned key material properties. For example, measurements showing the effect of film porosity on dielectric constant and thermal and mechanical properties is presented. This data, as well as that for other material types, demonstrates the tradeoffs between dielectric constant and thermomechanical properties that are often made during the course of material development.

Process integration of Cu metallization and ultra low k (k=2.2)

2003 ◽  
Author(s):  
Chuan-cheng Cheng ◽  
Wei-jen Hsia ◽  
J. Pallinti ◽  
S. Neumann ◽  
J. Koh ◽  
...  
Keyword(s):  
Process Integration ◽  
Cu Metallization ◽  
Low K

Assessment of Reliability of cap layers used in Cu-Black DiamondTM Interconnects

2003 ◽  
Vol 766 ◽  
Author(s):  
Ahila Krishnamoorthy ◽  
N.Y. Huang ◽  
Shu-Yunn Chong
Keyword(s):  
Dielectric Layer ◽  
Dielectric Breakdown ◽  
Copper Ions ◽  
Dielectric Strength ◽  
Time Dependent ◽  
Breakdown Field ◽  
Field Range ◽  
Time Dependent Dielectric Breakdown ◽  
Voltage Ramp ◽  
Low K

AbstractBlack DiamondTM. (BD) is one of the primary candidates for use in copper-low k integration. Although BD is SiO2 based, it is vastly different from oxide in terms of dielectric strength and reliability. One of the main reliability concerns is the drift of copper ions under electric field to the surrounding dielectric layer and this is evaluated by voltage ramp (V-ramp) and time dependent dielectric breakdown (TDDB). Metal 1 and Metal 2 intralevel comb structures with different metal widths and spaces were chosen for dielectric breakdown studies. Breakdown field of individual test structures were obtained from V-ramp tests in the temperature range of 30 to 150°C. TDDB was performed in the field range 0.5 – 2 MV/cm. From the leakage between combs at the same level (either metal 1 or metal 2) Cu drift through SiC/BD or SiN/BD interface was characterized. It was found that Cu/barrier and barrier/low k interfaces functioned as easy paths for copper drift thereby shorting the lines. Cu/SiC was found to provide a better interface than Cu/SiN.

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