Methods And Needs For Low K Material Research

1995 ◽  
Vol 381 ◽  
Author(s):  
Chiu H. Ting ◽  
Thomas E. Seidel
Keyword(s):  
High Performance ◽  
Process Integration ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Material Research ◽  
Material Development ◽  
Device Reliability ◽  
New Material ◽  
Speed Up ◽  
Low K

AbstractFor several years the industry has recognized the need of developing low k dielectric material and high conductivity metal for high performance interconnect. Low k dielectric will impact both power and delay favorably, while higher conductivity metal will reduce delay time. In order to be useful, new low k dielectric materials must be carefully characterized for their electrical, chemical, thermal and mechanical properties. In addition, their impact on process integration, fabrication cost and device reliability must also be considered. Since the gestation period for introducing a new material is very long, a set of standard testing methodologies are required to speed up the development process. This review will discuss various material options and the progress of material development and characterization methodologies. Example results will be provided for assessing these parameters.

Structure-Property Correlation in Low K Dielectric Materials

1999 ◽  
Vol 565 ◽  
Author(s):  
Michael Morgen ◽  
Jie-Hua Zhao ◽  
Michael Hay ◽  
Taiheui Cho ◽  
Paul S. Ho
Keyword(s):  
Dielectric Constant ◽  
Mechanical Stability ◽  
Process Integration ◽  
Dielectric Materials ◽  
Thermomechanical Properties ◽  
Low Dielectric Constant ◽  
Structure Property ◽  
Material Development ◽  
Low Dielectric ◽  
Low K

AbstractIn recent years there have been widespread efforts to identify low dielectric constant materials that can satisfy a number of diverse performance requirements necessary for successful integration into IC devices. This has led to extensive efforts to develop low k materials and the associated process integration. A particularly difficult challenge for material development has been to find the combination of low dielectric constant and good thermal and mechanical stability. In this paper recent characterization results for low k materials performed at the University of Texas will be reviewed, with an emphasis on the relationship of chemical structure to the aforementioned key material properties. For example, measurements showing the effect of film porosity on dielectric constant and thermal and mechanical properties is presented. This data, as well as that for other material types, demonstrates the tradeoffs between dielectric constant and thermomechanical properties that are often made during the course of material development.

High Reliability and Thermal Performance FCBGA Package

2007 ◽  
Author(s):  
Gino Hung ◽  
Ho-Yi Tsai ◽  
Chun An Huang ◽  
Steve Chiu ◽  
C. S. Hsiao
Keyword(s):  
Thermal Performance ◽  
High Performance ◽  
Flip Chip ◽  
Dielectric Material ◽  
High Reliability ◽  
Lead Free ◽  
Molding Process ◽  
Molding Compound ◽  
Reliability Performance ◽  
Low K

A high reliability and high thermal performance molding flip chip ball grid arrays structure which was improved from Terminator FCBGA®. (The structure are shown as Fig. 1) It has many advantages, like better coplanarity, high through put (multi pes for each shut of molding process), low stress, and high thermal performance. In conventional flip chip structure, underfill dispenses and cure processes are a bottleneck due to low through put (dispensing unit by unit). For the high performance demand, large package/die size with more integrated functions needs to meet reliability criteria. Low k dielectric material, lead free bump especially and the package coplanarity are also challenges for package development. Besides, thermal performance is also a key concern with high power device. From simulation and reliability data, this new structure can provide strong bump protection and reach high reliability performance and can be applied for low-K chip and all kind of bump composition such as tin-lead, high lead, and lead free. Comparing to original Terminator FCBGA®, this structure has better thermal performance because the thermal adhesive was added between die and heat spreader instead of epoxy molding compound (EMC). The thermal adhesive has much better thermal conductivity than EMC. Furthermore, this paper also describes the process and reliability validation result.

Overview Of Process Integration Issues For Low K Dielectrics

1998 ◽  
Vol 511 ◽  
Author(s):  
R. H. Havemann ◽  
M. K. Jain ◽  
R. S. List ◽  
A. R. Ralston ◽  
W-Y. Shih ◽  
...  
Keyword(s):  
Large Scale ◽  
Process Integration ◽  
Functional Integration ◽  
Dielectric Materials ◽  
Limiting Factor ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
Rc Delay ◽  
Low K

ABSTRACTThe era of silicon Ultra-Large-Scale-Integration (ULSI) has spurred an everincreasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. Both interconnect resistance and capacitance play key roles in overall performance, but modeling simulations have highlighted the importance of reducing parasitic capacitance to manage crosstalk, power dissipation and RC delay. New dielectric materials with lower permittivity (k) are needed to meet this challenge. This paper summarizes the process integration and reliability issues associated with the use of novel low k materials in multilevel interconnects.

Process Integration issues for Interlevel Dielectric Materials for Sub-quarter Micron Silicon Integrated Circuits

1998 ◽  
Vol 511 ◽  
Author(s):  
Vijay Parihar ◽  
R. Singh
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Process Integration ◽  
Dielectric Materials ◽  
New Approach ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Silicon Integrated Circuits ◽  
Processing Techniques ◽  
Low K

ABSTRACTThe continued miniaturization towards sub-quarter micron feature size mandates the search for low dielectric constant interlayer dielectric materials. A large number of materials and processing techniques has been suggested, but so far none of the proposed dielectric materials as well as processing techniques have been integrated into standard integrated circuit processing. In this paper, a new approach has been formulated for integration of low-k dielectric materials for future integrated circuits.

UV-Raman Microscopy on the Analysis of Ultra-Low-K Dielectric Materials on Patterned Wafers

2013 ◽  
Vol 740 ◽  
pp. 680-689 ◽  
Author(s):  
Maggie Y.M. Huang ◽  
Jeffrey C.K. Lam ◽  
Hao Tan ◽  
Tsu Hau Ng ◽  
Mohammed Khalid Bin Dawood ◽  
...  
Keyword(s):  
Silicon Oxide ◽  
Dielectric Breakdown ◽  
Process Integration ◽  
Dielectric Materials ◽  
Raman Microscopy ◽  
Three Dimension ◽  
Cu Metallization ◽  
Patterned Wafers ◽  
Uv Raman ◽  
Low K

With the shrinkage of the IC device dimension, Cu and ultra-low-k dielectric were introduced into IC devices to reduce the RC delay. Ultra-low-k dielectrics generally suffer more damage than silicon oxide dielectric during process integration and subsequently cause reliability degradation. Therefore, ultra-low-k damage characterization on Cu damascene structures is of great importance to understand the damage mechanisms. This paper describes the application of UV-Raman microscopy with enhanced spatial resolution and signal sensitivity for characterizing ultra-low-k dielectric in the three-dimension structure of Cu metallization with nanometer feature size. It shows UV-Raman technique has an advantage in analyzing ultra-low-k layer on patterned wafer and extracting ultra-low-k signals from Cu/ultra-low-k mixed structure. UV-Raman is also effective to characterize the ultra-low-k degradation for ultra-low-k related reliability analysis by time dependent dielectric breakdown (TDDB) test.

METAL FIBERS FOR NEW AIRCRAFT ENGINE MATERIALS

2020 ◽  
pp. 23-34
Author(s):  
D.P. Farafonov ◽  
◽  
M.M. Serov ◽  
A.Yu. Patrushev ◽  
N.E. Leshchev ◽  
...  
Keyword(s):  
Material Science ◽  
Extraction Method ◽  
High Performance ◽  
Aircraft Engine ◽  
Federal State ◽  
Material Research ◽  
Federal State Unitary Enterprise ◽  
Environmental Characteristics ◽  
New Material

Presents the results of work carried out at the Federal state unitary enterprise «VIAM» in the framework of a new material science direction – metallurgy of metal fibers. This work was made possible by the development of a method for producing metal fibers called the hanging melt drop extraction method (EUCR). This method is high-performance and allows you to obtain fibers from almost any material. Research has shown that it is possible to improve the performance and environmental characteristics of modern and advanced engines by introducing new classes of materials based on metal fibers.

UV-Raman Microscopy on the Analysis of Ultra-Low-k Dielectric Materials on Patterned Wafers

2013 ◽  
Author(s):  
Maggie Y.M. Huang ◽  
Tsu Hau Ng ◽  
Hao Tan ◽  
Mohammed Khalid Bin Dawood ◽  
Pik Kee Tan ◽  
...  
Keyword(s):  
Silicon Oxide ◽  
Dielectric Breakdown ◽  
Process Integration ◽  
Dielectric Materials ◽  
Raman Microscopy ◽  
Three Dimension ◽  
Cu Metallization ◽  
Patterned Wafers ◽  
Uv Raman ◽  
Low K

Abstract With the shrinkage of the IC device dimensions, Cu and ultra-low-k dielectric were introduced into IC devices to reduce RC delay. Ultra-low-k dielectrics generally suffer more damage than silicon oxide dielectric during process integration and subsequently cause reliability degradation. Therefore, ultra-low-k damage characterization on Cu damascene structures is of great importance to understand the damage mechanisms. This paper describes the application of UV-Raman microscopy with enhanced spatial resolution and signal sensitivity for characterizing ultra-low-k dielectric in the three-dimension structure of Cu metallization with nanometer feature size. It shows UV-Raman technique has an advantage in analyzing ultra-low-k layer on patterned wafer and extracting ultra-low-k signals from Cu/ultra-low-k mixed structure. UV-Raman is also effective to characterize the ultra-low-k degradation for ultra-low-k related reliability analysis by time dependent dielectric breakdown (TDDB) test.

Critical and Sub-critical Debonding in Nano-clustering Porous Low-k Films

2006 ◽  
Vol 914 ◽  
Author(s):  
Ryan Scott Smith ◽  
C. J. Uchibori ◽  
P. S. Ho ◽  
T. Nakamura
Keyword(s):  
Molecular Structure ◽  
Crack Growth ◽  
Adhesion Strength ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Growth Data ◽  
Critical Crack ◽  
Ambient Temperatures ◽  
Technology Roadmap ◽  
Low K

AbstractVery few porous low-k dielectric materials meet the basic requirements for integration into the back end of the line (BEOL) metallization. According to the International Technology Roadmap for Semiconductors, 2005, candidates for the 45 nm node need a k<2.2 and a minimum adhesion strength of 5 J/m2. Recently, a low-k dielectric material was developed, called nano-clustered silica (NCS). It is a spin-on glass with k<2.3. NCS is constitutively porous, with a micro- and mesopore size of ~2.8 nm. The first reported adhesion strength of this material was 10+ J/m2. We investigated the nature of the adhesive strength of NCS by critical and sub-critical fracture and Fourier Transform IR Spectroscopy (FTIR). The four-point bend technique and a mixed-mode double cantilever beam technique were employed. The sub-critical crack growth studies were performed in humid environments and ambient temperatures. Different post-treatments were used on NCS to achieve different molecular structure, as measured with FTIR. A correlation between molecular structure and critical adhesion energy was found. Atomistic parameters were calculated from the sub-critical crack growth data. A dependency of fracture behavior on post-treatment and, therefore, structure was observed.

Interfacial Adhesion Study of Porous Low-K Dielectrics to CVD Barrier Layers

2002 ◽  
Vol 716 ◽  
Author(s):  
Jeffrey A. Lee ◽  
Jeffrey T. Wetzel ◽  
Caroline Merrill ◽  
Paul S. Ho
Keyword(s):  
Mechanical Properties ◽  
Fracture Energy ◽  
Barrier Layer ◽  
Dielectric Material ◽  
Measurement Data ◽  
Dielectric Materials ◽  
Cohesive Failure ◽  
University Of Texas ◽  
Barrier Layers ◽  
Low K

AbstractThe present paper discusses the four-point bending technique employed at The University of Texas at Austin (UT Austin) to characterize adhesion strength of ultra low-k dielectric materials to CVD barrier layers. Adhesion energy between an ultra low-k dielectric material and a barrier layer was measured as a function of porosity (2.0 < k < 2.3). It was found that the fracture energy decreases with the dielectric constant, which correlates with mechanical properties such as Young's modulus and hardness. Adhesion measurement data was also obtained for different lowk / barrier layer interfaces. The independence of interfacial fracture energy on the type of interface suggests that cohesive failure occurs in the low-k material layer and not at the interface. In addition, the very low fracture energies (G < 3 J/2) confirm the weak mechanical properties of such highly porous materials. Experimental results are illustrated with analysis of failure surfaces using Auger Electron Spectroscopy and Scanning Electron Microscopy.

scholarly journals The Ultra-Low-k Dielectric Materials for Performance Improvement in Coupled Multilayer Graphene Nanoribbon Interconnects

Electronics ◽  
2019 ◽  
Vol 8 (8) ◽  
pp. 849 ◽  
Author(s):  
Peng Xu ◽  
Zhongliang Pan ◽  
Zhenhua Tang
Keyword(s):  
Delay Time ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Dielectric Medium ◽  
Graphene Nanoribbon ◽  
Noise Voltage ◽  
Multilayer Graphene ◽  
Crosstalk Noise ◽  
Characteristic Analysis ◽  
Low K

The ultra-low-k dielectric material replacing the conventional SiO2 dielectric medium in coupled multilayer graphene nanoribbon (MLGNR) interconnects is presented. An equivalent distributed transmission line model of coupled MLGNR interconnects is established to derive the analytical expressions of crosstalk delay, transfer gain, and noise output for 7.5 nm technology node at global level, which take the in-phase and out-of-phase crosstalk into account. The results show that by replacing the SiO2 dielectric mediums with the nanoglass, the maximum reduction of delay time and peak noise voltage are 25.202 ns and 0.102 V for an interconnect length of 3000 µm, respectively. It is demonstrated that the ultra-low-k dielectric materials can significantly reduce delay time and crosstalk noise and increase transfer gain compared with the conventional SiO2 dielectric medium. Moreover, it is found that the coupled MLGNR interconnect under out-of-phase mode has a larger crosstalk delay and a lesser transfer gain than that under in-phase mode, and the peak noise voltage increases with the increase of the coupled MLGNR interconnect length. The results presented in this paper would be useful to aid in the enhancement of performance of on-chip interconnects and provide guidelines for signal characteristic analysis of MLGNR interconnects.

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