Process Integration issues for Interlevel Dielectric Materials for Sub-quarter Micron Silicon Integrated Circuits

1998 ◽  
Vol 511 ◽  
Author(s):  
Vijay Parihar ◽  
R. Singh
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Process Integration ◽  
Dielectric Materials ◽  
New Approach ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Silicon Integrated Circuits ◽  
Processing Techniques ◽  
Low K

ABSTRACTThe continued miniaturization towards sub-quarter micron feature size mandates the search for low dielectric constant interlayer dielectric materials. A large number of materials and processing techniques has been suggested, but so far none of the proposed dielectric materials as well as processing techniques have been integrated into standard integrated circuit processing. In this paper, a new approach has been formulated for integration of low-k dielectric materials for future integrated circuits.

Novel Materials as Interlayer Low-K Dielectrics for CMOS Interconnect Applications

2011 ◽  
Vol 110-116 ◽  
pp. 5380-5383
Author(s):  
Tejas R. Naik ◽  
Veena R. Naik ◽  
Nisha P. Sarwade
Keyword(s):  
Dielectric Constant ◽  
Integrated Circuits ◽  
Dielectric Materials ◽  
Low Dielectric Constant ◽  
Interlayer Dielectric ◽  
Novel Materials ◽  
Low Dielectric ◽  
Processing Properties ◽  
New Generation ◽  
Low K

Scaling down the integrated circuits has resulted in the arousal of number of problems like interaction between interconnect, crosstalk, time delay etc. These problems can be overcome by new designs and by use of corresponding novel materials, which may be a solution to these problems. In the present paper we try to put forward very recent development in the use of novel materials as interlayer dielectrics (ILDs) having low dielectric constant (k) for CMOS interconnects. The materials presented here are porous and hybrid organo-inorganic new generation interlayer dielectric materials possessing low dielectric constant and better processing properties.

scholarly journals The Evolution of Organosilicon Precursors for Low-k Interlayer Dielectric Fabrication Driven by Integration Challenges

Materials ◽  
2021 ◽  
Vol 14 (17) ◽  
pp. 4827
Author(s):  
Nianmin Hong ◽  
Yinong Zhang ◽  
Quan Sun ◽  
Wenjie Fan ◽  
Menglu Li ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Data Storage ◽  
Integrated Circuit ◽  
Porous Silica ◽  
Dielectric Materials ◽  
Interlayer Dielectric ◽  
Damascene Process ◽  
Key Issues ◽  
Deposition Processes ◽  
Low K

Since the application of silicon materials in electronic devices in the 1950s, microprocessors are continuously getting smaller, faster, smarter, and larger in data storage capacity. One important factor that makes progress possible is decreasing the dielectric constant of the insulating layer within the integrated circuit (IC). Nevertheless, the evolution of interlayer dielectrics (ILDs) is not driven by a single factor. At first, the objective was to reduce the dielectric constant (k). Reduction of the dielectric constant of a material can be accomplished by selecting chemical bonds with low polarizability and introducing porosity. Moving from silicon dioxide, silsesquioxane-based materials, and silica-based materials to porous silica materials, the industry has been able to reduce the ILDs’ dielectric constant from 4.5 to as low as 1.5. However, porous ILDs are mechanically weak, thermally unstable, and poorly compatible with other materials, which gives them the tendency to absorb chemicals, moisture, etc. All these features create many challenges for the integration of IC during the dual-damascene process, with plasma-induced damage (PID) being the most devastating one. Since the discovery of porous materials, the industry has shifted its focus from decreasing ILDs’ dielectric constant to overcoming these integration challenges. More supplementary precursors (such as Si-C-Si structured compounds), deposition processes (such as NH3 plasma treatment), and post porosity plasma protection treatment (P4) were invented to solve integration-related challenges. Herein, we present the evolution of interlayer dielectric materials driven by the following three aspects, classification of dielectric materials, deposition methods, and key issues encountered and solved during the integration phase. We aim to provide a brief overview of the development of low-k dielectric materials over the past few decades.

Determination of the Modulus and Hardness of Spin-on Zeolite Low-K Thin Films

2005 ◽  
Vol 880 ◽  
Author(s):  
Mark Johnson ◽  
Zijian Li ◽  
Yushan Yan ◽  
Junlan Wang
Keyword(s):  
Thin Films ◽  
Integrated Circuit ◽  
Material Selection ◽  
Dielectric Materials ◽  
Dielectric Constants ◽  
Depth Sensing ◽  
New Class ◽  
Low Dielectric ◽  
Pure Silica ◽  
Low K

AbstractWith the semiconductor technologies continuously pushing the miniaturization limits, there is a growing interest in developing novel low dielectric constant (low-k) materials to replace traditional dense SiO2 based insulators. In order to survive the multi-step integration process and provide reliable material and structure for the desired integrated circuit (IC) functions, the new low-k materials have to be mechanically strong and stable. Thus the material selection and mechanical characterization are vital in the successful development of next generation low-k dielectrics. A new class of low-k dielectric materials, nanoporous pure-silica zeolite, is prepared in thin films using IC compatible spin coating process and characterized using depth sensing nanoindentation technique. The elastic modulus measurements of the zeolite thin films are found to be significantly higher than that of other porous silicates with similar porosity and dielectric constants. Correlations of the mechanical, microstructural and electrical properties are discussed in detail.

Structure-Property Correlation in Low K Dielectric Materials

1999 ◽  
Vol 565 ◽  
Author(s):  
Michael Morgen ◽  
Jie-Hua Zhao ◽  
Michael Hay ◽  
Taiheui Cho ◽  
Paul S. Ho
Keyword(s):  
Dielectric Constant ◽  
Mechanical Stability ◽  
Process Integration ◽  
Dielectric Materials ◽  
Thermomechanical Properties ◽  
Low Dielectric Constant ◽  
Structure Property ◽  
Material Development ◽  
Low Dielectric ◽  
Low K

AbstractIn recent years there have been widespread efforts to identify low dielectric constant materials that can satisfy a number of diverse performance requirements necessary for successful integration into IC devices. This has led to extensive efforts to develop low k materials and the associated process integration. A particularly difficult challenge for material development has been to find the combination of low dielectric constant and good thermal and mechanical stability. In this paper recent characterization results for low k materials performed at the University of Texas will be reviewed, with an emphasis on the relationship of chemical structure to the aforementioned key material properties. For example, measurements showing the effect of film porosity on dielectric constant and thermal and mechanical properties is presented. This data, as well as that for other material types, demonstrates the tradeoffs between dielectric constant and thermomechanical properties that are often made during the course of material development.

The Effect of Alkaline Slurry on Low-K Film

2011 ◽  
Vol 295-297 ◽  
pp. 1621-1624
Author(s):  
Yi Hu ◽  
Yu Ling Liu ◽  
Li Ran Wang ◽  
Xiao Yan Liu ◽  
Yan Gang He
Keyword(s):  
Dielectric Properties ◽  
Time Delay ◽  
Integrated Circuits ◽  
Process Integration ◽  
Process Conditions ◽  
Static Test ◽  
Low Dielectric ◽  
Chemical Mechanical Polishing Process ◽  
The Impact ◽  
Low K

As the integrated circuits developing, the line-width and space between the metal interconnection are shrinking. This increases the RC time delay. To reduce the RC time delay, the low dielectric constant (low-k) material was introduced in the ICs. For process integration considerations, the impact of electronic characters was investigated. In this paper, both static test and CMP(chemical mechanical polishing) process conditions were executed on the low-kmaterial black diamond (BD) with slurry,which was explored by Hebei University of Technology. The slurry was utilized to evaluate the effect on the dielectric properties of BD films. Electrical analyses have shown dielectric properties of BD films would not be degraded during these processes. The static test was dipping the low–k material (BD)in the slurry for 30s and 2minutes, and the results showed the capacitance changed from 3.01to3.40 when dipping in 30s ,and the value reached 3.71 when dipping 2minutes. The resistance changed from 2.9-2.95 to 3.27-3.33 in 30s,and reached 3.57-3.63 in 2 minutes. The result of CMP process showed that the capacitance of five dots , which were selected on the BD film, changed from 2.94-2.98to 2.99-3.05. The dielectric integrity of lowkBD films after CMP process remained at an acceptable region to meet requires of multilevelinterconnection.

C4 EM and CPI Reliability Benefits and Process Challenges of FBEOL Integration Changes Implemented in Lead-free C4 Products

2015 ◽  
Vol 2015 (1) ◽  
pp. 000787-000792
Author(s):  
E. Misra ◽  
T. Wassick ◽  
I. Melville ◽  
K. Tunga ◽  
D. Questad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Lead Free ◽  
Solder Interconnects ◽  
Design Changes ◽  
Modeling Data ◽  
Free Solder ◽  
Low K

The introduction of low-k & ultra-low-k dielectrics, lead-free (Pb-free) solder interconnects or C4's, and organic flip-chip laminates for integrated circuits have led to some major reliability challenges for the semiconductor industry. These include C4 electromigration (EM) and mechanical failures induced with-in the Si chip due to chip-package interactions (CPI). In 32nm technology, certain novel design changes were evaluated in the last Cu wiring level and the Far Back End of Line levels (FBEOL) to strategically re-distribute the current more uniformly through the Pb-free C4 bumps and therefore improve the C4 EM capabilities of the technology. FBEOL process integration changes, such as increasing the thickness of the hard dielectric (SiNx & SiOx) and reducing the final via diameter, were also evaluated for reducing the mechanical stresses in the weaker BEOL levels and mitigating potential risks for mechanical failures within the Si chip. The supporting white-bump, C4 EM and electrical/mechanical modeling data that demonstrates the benefits of the design and integration changes will be discussed in detail in the paper. Some of the key processing and integration challenges observed due to the design and process updates and the corresponding mitigation steps taken will also be discussed.

Intrinsic low dielectric behaviour of a highly thermally stable Sr-based metal–organic framework for interlayer dielectric materials

2014 ◽  
Vol 2 (19) ◽  
pp. 3762-3768 ◽  
Author(s):  
Muhammad Usman ◽  
Cheng-Hua Lee ◽  
Dung-Shing Hung ◽  
Shang-Fan Lee ◽  
Chih-Chieh Wang ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Metal Organic Framework ◽  
Dielectric Materials ◽  
Low Dielectric Constant ◽  
Water Molecules ◽  
Compound A ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Metal Organic ◽  
Organic Framework

A Sr-based metal–organic framework exhibits an intrinsic low dielectric constant after removing the water molecules. A low dielectric constant and high thermal stability make this compound a candidate for use as a low-k material.

Thermal conductivity study of porous low K dielectric materials

1999 ◽  
Vol 565 ◽  
Author(s):  
Chuan Hu ◽  
Michael Morgen ◽  
Paul S. Ho ◽  
Anurag Jain ◽  
William. N. Gill ◽  
...  
Keyword(s):  
Thermal Conductivity ◽  
Dielectric Materials ◽  
Porous Films ◽  
Low Dielectric ◽  
Omega Method ◽  
3 Omega ◽  
Low Dielectric Constant Materials ◽  
Low K ◽  
Method Analysis

AbstractA quantitative characterization of the thermal properties is required to assess the thermal performance of low dielectric constant materials. Recently we have developed a technique based on the 3-omega method for measuring the thermal conductivity of porous dielectric thin films. In this paper we present the results on the measurements of thermal conductivity of thin porous films using this method. A finite element method analysis is used to evaluate the approximations used in the measurement. Two porosity-weighted thermal resistor models are proposed to interpret the results. By studying the dependence of the thermal conductivity on porosity, we are able to discuss the scaling rule of thermal conductivity. Additionally, a steady state layered heater model is used for evaluating the significance of introducing porous ILDs into an interconnect structure.

Designing Ultra Low-k Dielectric Materials for Ease of Patterning

2010 ◽  
Vol 1249 ◽  
Author(s):  
George Andrew Antonelli ◽  
Gengwei Jiang ◽  
Mandyam Sriram ◽  
Kaushik Chattopadhyay ◽  
Wei Guo ◽  
...  
Keyword(s):  
Inductively Coupled Plasma ◽  
Ion Beam ◽  
Plasma Reactor ◽  
Dielectric Materials ◽  
Dielectric Constants ◽  
Interlayer Dielectric ◽  
Inductively Coupled ◽  
Inductively Coupled Plasma Reactor ◽  
Low K

AbstractOrganosilicate materials with dielectric constants (k) ranging from 3.0 to 2.2 are in production or under development for use as interlayer dielectric materials in advanced interconnect logic technology. The dielectric constant of these materials is lowered through the addition of porosity which lowers the film density, making the patterning of these materials difficult. The etching kinetics and surface roughening of a series of low-k dielectric materials with varying porosity and composition were investigated as a function of ion beam angle in a 7% C4F8/Ar chemistry in an inductively-coupled plasma reactor. A similar set of low-k samples were patterned in a single damascene scheme. With a basic understanding of the etching process, we will show that it is possible to proactively design a low-k material that is optimized for a given patterning. A case study will be used to illustrate this point.

Up Close: MIT's Ceramics Manufacturing and Process Integration Laboratory

MRS Bulletin ◽  
1987 ◽  
Vol 12 (7) ◽  
pp. 91-94
Author(s):  
Richard L. Pober ◽  
Elizabeth A. Thomson
Keyword(s):  
Integrated Circuit ◽  
Manufacturing Systems ◽  
New Technologies ◽  
Process Integration ◽  
Basic Research ◽  
Massachusetts Institute Of Technology ◽  
Short Period ◽  
Manufacturing Productivity ◽  
Institute Of Technology ◽  
Processing Techniques

In a relatively short period of time ceramics have become the key elements to a variety of new technologies, including integrated circuit substrates, artificial limbs, turbocharger rotors, and, of course, superconductors. By and large, however, they have not met their potential. Though advances in basic research are responsible for the breakthroughs so far, no extensive work has been done to establish the manufacturing paradigms necessary for the production of reliable, reproducible materials.The new Ceramics Manufacturing and Process Integration Laboratory (CMPIL) at the Massachusetts Institute of Technology was conceived to address this need. As a logical extension of the science-based Ceramics Processing Research Laboratory (CPRL), also at MIT, the CMPIL will “test” fundamental ideas as they relate to ceramics manufacturing. The goal is to create a hands-on “research factory,” complete with manufactured product, to make an impact on manufacturing productivity and teach students, staff, and visiting scientists the principles that control ceramics manufacturing systems. Other thrusts include developing innovative processing techniques and collecting operating data that will ultimately be transferred to industry.

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