Fabrication Process for On-Board Geometries Using a Polymer Composite-Based Selective Metallization for Next-Generation Electronics Packaging

Advancements in production techniques in PCB manufacturing industries are still required as compared to silicon-ICs fabrications. One of the concerned areas in PCBs fabrication is the use of conventional methodologies for metallization. Most of the manufacturers are still using the traditional Copper (Cu) laminates on the base substrate and patterning the structures using lithography processes. As a result, significant amounts of metallic parts are etched away during any mass production process, causing unnecessary disposables leading to pollution. In this work, a new approach for Cu metallization is demonstrated with considerable step-reducing pattern-transfer mechanism. In the fabrication steps, a seed layer of covalent bonded metallization (CBM) chemistry on top of a dielectric epoxy resin is polymerized using actinic radiation intensity of a 375 nm UV laser source. The proposed method is capable of patterning any desirable geometries using the above-mentioned surface modification followed by metallization. To metallize the patterns, a proprietary electroless bath has been used. The metallic layer grows only on the selective polymer-activated locations and thus is called selective metallization. The highlight of this production technique is its occurrence at a low temperature (20–45 °C). In this paper, FR-4 as a base substrate and polyurethane (PU) as epoxy resin were used to achieve various geometries, useful in electronics packaging. In addition, analysis of the process parameters and some challenges witnessed during the process development are also outlined. As a use case, a planar inductor is fabricated to demonstrate the application of the proposed technique.

Laponite-Mediated Copper Metallization by Palladium Intercalation

An alternative catalytic method was employed using the reduction of Pd ions on the surface of cetyltrimethylammonium bromide (CTAB) treated laponite to initiate the electroless plating of copper; the deposition features of the Pd nanoparticles produced were investigated in detail. Results indicated intercalation and reduction of Pd nanoparticles occurred at room temperature and involved interaction between the laponite and the cetyltrimethylammonium cationic templates. Organic species and amount on laponite were optimized to adjust silicate platelet interlayer distances and platelet organophilic properties. Intercalation of Pd nanoparticles occurred between the magnesium silicate layers of laponite and this was dependent on pre-treatment and impregnation times. As impregnation is a method of producing heterogeneous catalysts, we considered Pd nanoparticles on laponite templates could catalyze the electroless deposition of Cu to initiate metallization. Cu films fabricated on laponite templates exhibited excellent surface roughness (˜1.7 nm) and low resistivity (˜3.42 μΩ). The devised approach enabled the facile formation of a network suitable for Cu metallization without causing substrate damage and produced metal surfaces with excellent flatness and resistivity.

Mechanical Properties and Diffusion Barrier Performance of CrWN Coatings Fabricated through Hybrid HiPIMS/RFMS

CrWN coatings were fabricated through a hybrid high-power impulse magnetron sputtering/radio-frequency magnetron sputtering technique. The phase structures, mechanical properties, and tribological characteristics of CrWN coatings prepared with various nitrogen flow ratios (fN2s) were investigated. The results indicated that the CrWN coatings prepared at fN2 levels of 0.1 and 0.2 exhibited a Cr2N phase, whereas the coatings prepared at fN2 levels of 0.3 and 0.4 exhibited a CrN phase. These CrWN coatings exhibited hardness values of 16.7–20.2 GPa and Young’s modulus levels of 268–296 GPa, which indicated higher mechanical properties than those of coatings with similar residual stresses prepared through conventional direct current magnetron sputtering. Face-centered cubic (fcc) Cr51W2N47 coatings with a residual stress of −0.53 GPa exhibited the highest wear and scratch resistance. Furthermore, the diffusion barrier performance of fcc CrWN films on Cu metallization was explored, and they exhibited excellent barrier characteristics up to 650 °C.

Fabrication of a Silicide Thermoelectric Module Employing Fractional Factorial Design Principles

Thermoelectric modules can be used in waste heat harvesting, sensing, and cooling applications. Here, we report on the fabrication and performance of a four-leg module based on abundant silicide materials. While previously optimized Mg2Si0.3Sn0.675Bi0.025 is used as the n-type leg, we employ a fractional factorial design based on the Taguchi methods mapping out a four-dimensional parameter space among Mnx-εMoεSi1.75−δGeδ higher manganese silicide compositions for the p-type material. The module is assembled using a scalable fabrication process, using a Cu metallization layer and a Pb-based soldering paste. The maximum power output density of 53 μW cm–2 is achieved at a hot-side temperature of 250 °C and a temperature difference of 100 °C. This low thermoelectric output is related to the high contact resistance between the thermoelectric materials and the metallic contacts, underlining the importance of improved metallization schemes for thermoelectric module assembly.

Nanometer-thin pure boron CVD layers as material barrier to Au or Cu metallization of Si

Metallization layers of aluminum, gold, or copper are shown to be protected from interactions with silicon substrates by thin boron layers grown by chemical-vapor deposition (CVD) at 450 °C. A 3-nm-thick B-layer was studied in detail. It formed the p+-anode region of PureB diodes that have a metallurgic junction depth of zero on n-type Si. The metals were deposited by electron-beam-assisted physical vapor deposition (EBPVD) at room temperature and annealed at temperatures up to 500 °C. In all cases, the B-layer was an effective material barrier between the metal and Si, as verified by practically unchanged PureB diode I–V characteristics and microscopy inspections of the deposited layers. For this result, it was required that the Si surface be clean before B-deposition. Any Si surface contamination was otherwise seen to impede a complete B-coverage giving, sometimes Schottky-like, current increases. For Au, room-temperature interactions with the Si through such pinholes in the B-layer were excessive after the 500 °C anneal.

Improvement of thermal stability of Ta-N film in Cu metallization by a Zr-Si interlayer

Ta-N (10 nm)/Zr (20 nm) film was grown on n-type (100) silicon wafer at various substrate temperatures in a rf magnetron sputtering system, followed by in situ deposition of Cu. The Cu/Ta-N/Zr/Si samples were subjected to thermal annealing up to 800 ℃ under the protection of pure nitrogen gas. In order to investigate the effect of insertion of a thin Zr layer under Ta-N film on Ta-N diffusion barrier performance in Cu metallization, Cu/Ta-N/Zr/Si contact system was characterized by X-ray diffraction (XRD), four-point probe (FPP) measurement, scanning electron microscopy (SEM), and Auger electron spectroscopy (AES) depth profile. The results reveal that the microstructure of Ta-N films deposited on Zr is amorphous at different substrate temperatures. The barrier breakdown temperature of Ta-N/Zr film is about 100°C higher than that of Ta-N. It can effectively prevent the diffusion of Cu after annealed at 800°C. The improvement of diffusion barrier performance may be due to the production of Zr-Si layer with low contact resistivity after annealed at 800°C.

Material Properties of Zr–Cu–Ni–Al Thin Films as Diffusion Barrier Layer

Due to the rapid increase in current density encountered in new chips, the phenomena of thermomigration and electromigration in the solder bump become a serious reliability issue. Currently, Ni or TiN, as a barrier layer, is widely academically studied and industrially accepted to inhibit rapid copper diffusion in interconnect structures. Unfortunately, these barrier layers are polycrystalline and provide inadequate protection because grain boundaries may presumably serve as fast diffusion paths for copper and could react to form Cu–Sn intermetallic compounds (IMCs). Amorphous metallic films, however, have the potential to be the most effective barrier layer for Cu metallization due to the absence of grain boundaries and immiscibility with copper. In this article, the diffusion properties, the strength of the interface between polycrystalline and amorphous ZrCuNiAl thin film, and the effects of quenching rate on the internal microstructures of amorphous metal films were individually investigated by molecular dynamics (MD) simulation. Moreover, experimental data of the diffusion process for three different cases, i.e., without barrier layer, with an Ni barrier layer, and with a Zr53Cu30Ni9Al8 thin film metallic glass (TFMG) barrier layer, were individually depicted. The simulation results show that, for ZrCuNiAl alloy, more than 99% of the amorphous phase at a quenching rate between 0.25 K/ps and 25 K/ps can be obtained, indicating that this alloy has superior glass-forming ability. The simulation of diffusion behavior indicated that a higher amorphous ratio resulted in better barrier performance. Moreover, a very small and uniformly distributed strain appears in the ZrCuNiAl layer in the simulation of the interfacial tension test; however, almost all the voids are initiated and propagated in the Cu layer. These phenomena indicate that the strength of the ZrCuNiAl/Cu interface and ZrCuNiAl layer is greater than polycrystalline Cu. Experimental results show that the Zr53Cu30Ni9Al8 TFMG layer exhibits a superior barrier effect. Almost no IMCs appear in this TFMG barrier layer even after aging at 125 °C for 500 h.