Detectability of Automotive Power MOSFET On-Resistance Failure at High Current Induced by Wafer Fab Process Excursion

2014 ◽  
Author(s):  
Yann Weber ◽  
Julien Goxe ◽  
Maris Castignolles
Keyword(s):  
Failure Analysis ◽  
Low Voltage ◽  
Fault Localization ◽  
Automotive Application ◽  
High Current ◽  
Process Variability ◽  
Power Mosfet ◽  
Wafer Fab ◽  
A Minor

Abstract This paper presents the meaningful consequence of a minor Wafer Fab process variability, generating on-resistance drift on low voltage vertical power N-MOSFETs dedicated to microhybrid automotive application. The originality of this paper concerns the necessity to use complementary failure analysis investigations needed to determine the origin of the failure without any possibilities to perform any fault localization. The results enabled implementation of corrections and improvement of test screening to protect customers.

A Sample Preparation Methodology for Effective Failure Analysis of Trench Power MOSFET

2013 ◽  
Author(s):  
Yan Li ◽  
S.K. Loh ◽  
C.Q. Chen ◽  
G.B. Ang ◽  
A.C.T. Quah ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Success Rate ◽  
Defect Detection ◽  
Fault Localization ◽  
Power Mosfet

Abstract This paper describes a sample preparation methodology for Trench Power MOSFET that significantly improved our failure analysis success rate for trench bottom defect. With precise fault localization and subsequent a unique physical failure analysis using parallel polishing method on Trench Power MOSFET, This enabled defect detection from the trench top to the trench bottom.

Detectability of automotive power MOSFET on-resistance failure at high current induced by Wafer Fab process excursion

2013 ◽  
Vol 53 (9-11) ◽  
pp. 1393-1398 ◽  
Author(s):  
Y. Weber ◽  
J. Goxe ◽  
M. Castignolles
Keyword(s):  
High Current ◽  
Power Mosfet ◽  
Wafer Fab

Advanced IR-OBIRCH Analysis Technique for High Isb Failure Analysis

2010 ◽  
Author(s):  
Kuo Hsiung Chen ◽  
Wen Sheng Wu ◽  
Yu Hsiang Shu ◽  
Jian Chan Lin
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Fault Localization ◽  
Resistance Change ◽  
The Real ◽  
Analysis Techniques ◽  
Analysis Technique ◽  
Leakage Failure ◽  
Failure Site

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.

A Sample Preparation on Decapsulation Methodology for Effective Failure Analysis on Thin Small Leadless (TSLP) Flip Chip Package with Copper Pillar (CuP) Bump Interconnect Technology

2014 ◽  
Author(s):  
Gwee Hoon Yen ◽  
Ng Kiong Kay
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Fault Localization ◽  
Cost Effective ◽  
Fault Isolation ◽  
Voltage Contrast ◽  
Interconnect Technology

Abstract Today, failure analysis involving flip chip [1] with copper pillar bump packaging technologies would be the major challenges faced by analysts. Most often, handling on the chips after destructive chemical decapsulation is extremely critical as there are several failure analysis steps to be continued such as chip level fault localization, chip micro probing for fault isolation, parallel lapping [2, 3, 4] and passive voltage contrast. Therefore, quality of sample preparation is critical. This paper discussed and demonstrated a quick, reliable and cost effective methodology to decapsulate the thin small leadless (TSLP) flip chip package with copper pillar (CuP) bump interconnect technology.

scholarly journals Synchronous Generator Rectification System Based on Double Closed-Loop Control of Backstepping and Sliding Mode Variable Structure

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1832
Author(s):  
Jinfeng Liu ◽  
Xin Qu ◽  
Herbert Ho-Ching Iu
Keyword(s):  
Closed Loop ◽  
Control Structure ◽  
Low Voltage ◽  
Sliding Mode ◽  
Variable Structure ◽  
Synchronous Generator ◽  
Closed Loop Control ◽  
High Current ◽  
Loop Control ◽  
Sliding Mode Variable Structure

Low-voltage and high-current direct current (DC) power supplies are essential for aerospace and shipping. However, its robustness and dynamic response need to be optimized further on some special occasions. In this paper, a novel rectification system platform is built with the low-voltage and high-current permanent magnet synchronous generator (PMSG), in which the DC voltage double closed-loop control system is constructed with the backstepping control method and the sliding mode variable structure (SMVS). In the active component control structure of this system, reasonable virtual control variables are set to obtain the overall structural control variable which satisfied the stability requirements of Lyapunov stability theory. Thus, the fast-tracking and the global adjustment of the system are realized and the robustness is improved. Since the reactive component control structure is simple and no subsystem has to be constructed, the SMVS is used to stabilize the system power factor. By building a simulation model and experimental platform of the 5 V/300 A rectification module based on the PMSG, it is verified that the power factor of the system can reach about 98.5%. When the load mutation occurs, the DC output achieves stability again within 0.02 s, and the system fluctuation rate does not exceed 2%.

A Low-Voltage Planar Power MOSFET With a Segmented JFET Region

2009 ◽  
Vol 56 (8) ◽  
pp. 1761-1766 ◽  
Author(s):  
Jacky C. W. Ng ◽  
Johnny K. O. Sin
Keyword(s):  
Low Voltage ◽  
Power Mosfet

A 12 to 1 V five phase interleaving GaN POL converter for high current low voltage applications

2014 ◽  
Author(s):  
Benjamin K. Rhea ◽  
Luke L. Jenkins ◽  
William E. Abell ◽  
Frank T. Werner ◽  
Christopher G. Wilson ◽  
...  
Keyword(s):  
Low Voltage ◽  
High Current
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