Debug and Fault Isolation of an RF/IF Circuit for 3G Cellular Applications With High Leakage: A Case Study

2002 ◽  
Author(s):  
Syd Wilson ◽  
Manoj Nair ◽  
Michael Vicker ◽  
Richard B. Meador ◽  
George Smoot ◽  
...  
Keyword(s):  
Leakage Current ◽  
Integrated Circuit ◽  
Photon Emission ◽  
Cost Effective ◽  
Fault Isolation ◽  
Cellular Phones ◽  
Third Generation ◽  
Mixed Signal ◽  
Emission Microscopy

Abstract First silicon of a cost effective, BICMOS mixed signal RF/IF integrated circuit (IC) for third generation (3G) cellular phones showed high leakage current on the analog receive supply pins in “battery save” mode. Our tasks were to identify and isolate the source of leakage and to fix the design. Alternate debug techniques were used to isolate the cause of the leakage and provide a solution after inconclusive results were obtained using photon emission microscopy,(1) and infrared microthermography techniques.

Failure Analysis of Sub-Micron Semiconductor Integrated Circuit Using Backside Photon Emission Microscopy

1999 ◽  
Author(s):  
Soon Lim ◽  
Jian Hua Bi ◽  
Lian Choo Goh ◽  
Soh Ping Neo ◽  
Sudhindra Tatti
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Photon Emission ◽  
Fault Isolation ◽  
Integrated Circuit Fabrication ◽  
Circuit Fabrication ◽  
Emission Microscopy ◽  
On Chip

Abstract The progress of modern day integrated circuit fabrication technology and packaging has made fault isolation using conventional emission microscopy via the top of the integrated circuit more difficult, if not impossible. This is primarily due to the use of increased levels and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution to this problem. This paper outlines the failure analysis of sub-micron silicon integrated circuits using backside photon emission microscopy. Sample preparation, practical difficulties encountered and case histories will be discussed.

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

2010 ◽  
Author(s):  
Sarven Ipek ◽  
David Grosjean
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Analysis Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

A Case Study of Defects Due to Process-Design Interaction in Nano Scale Technology

2007 ◽  
Author(s):  
Hung-Sung Lin ◽  
Ying-Chin Hou ◽  
Juimei Fu ◽  
Mong-Sheng Wu ◽  
Vincent Huang ◽  
...  
Keyword(s):  
Liquid Crystal ◽  
Circuit Design ◽  
Process Design ◽  
Integrated Circuit ◽  
Photon Emission ◽  
Integrated Circuit Design ◽  
Nano Scale ◽  
Leakage Path ◽  
Related Defect

Abstract The difficulties in identifying the precise defect location and real leakage path is increasing as the integrated circuit design and process have become more and more complicated in nano scale technology node. Most of the defects causing chip leakage are detectable with only one of the FA (Failure Analysis) tools such as LCD (Liquid Crystal Detection) or PEM (Photon Emission Microscope). However, due to marginality of process-design interaction some defects are often not detectable with only one FA tool [1][2]. This paper present an example of an abnormal power consumption process-design interaction related defect which could only be detected with more advanced FA tools.

Debugging Phase-Locked Loop Failures in Integrated Circuit Products

2014 ◽  
Author(s):  
S.H. Goh ◽  
Wendy Lau ◽  
B.L. Yeoh ◽  
H.W. Ho ◽  
G.F. You ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Frequency Control ◽  
Photon Emission ◽  
Building Blocks ◽  
Phase Locked Loop ◽  
Fault Isolation ◽  
Loop Control ◽  
Isolation Techniques ◽  
Loop Control System ◽  
Specific Frequency

Abstract A phase-locked loop (PLL) is commonly used in integrated circuit devices for frequency control. In a finished product, it comprises of sub-building blocks operating in a closed-loop control system which do not have register readback or test access points for easy debugging. Failure analysis becomes a challenge. This paper demonstrates the inherent limitation of relying only on dynamic fault isolation techniques, in specific frequency mapping for PLL failure debug. A systematic debug approach that combines volume failure characterization on test, additional characterization using dynamic photon emission and design simulation is then presented. Results are obtained on a 28 nm node device.

Scanning SQUID Microscopy for Die Level Fault Isolation

2002 ◽  
Author(s):  
David P. Vallett
Keyword(s):  
Liquid Crystal ◽  
Photon Emission ◽  
Fault Isolation ◽  
Induced Voltage ◽  
Sem Images ◽  
Thermal Mapping ◽  
Localized Defects ◽  
Emission Microscopy ◽  
Scanning Squid ◽  
Scanning Squid Microscopy

Abstract This paper presents detailed results of scanning SQUID microscopy (SSM) analyses performed on the frontside and backside of both loose and packaged die. Optical and SEM images of localized defects are shown. Comparisons with alternative physical fault isolation (PFI) techniques like liquid crystal (LC), Schlieren thermal mapping (STM), temperature induced voltage alteration (TIVA), and photon emission microscopy (PEM) are included. Finally, limitations with and potential improvements for die level SSM are also discussed.

Enhancing Point Defect Isolation by Using Ionizing Radiation

2019 ◽  
Author(s):  
Douglas J. Martin ◽  
Matthew J. Gadlage ◽  
Wai-Yat Leung ◽  
Jeffrey L. Titus
Keyword(s):  
Ionizing Radiation ◽  
Integrated Circuit ◽  
Focused Ion Beam ◽  
High Reliability ◽  
Ion Beam ◽  
Photon Emission ◽  
Fault Isolation ◽  
Oxide Semiconductor ◽  
Carrier Injection ◽  
Failure Site

Abstract An application-specific integrated circuit (ASIC) for a high reliability application is found to have a missing sidewall spacer in a single transistor. Manufacturer burn-in and standard component electrical tests do not capture this defect. The defect manifests after exposure to ionizing radiation. Photon emission microscopy (PEM), laser voltage imaging (LVI), and laserassisted device alteration (LADA) are used to isolate the failure site. At the failure site a focused ion beam (FIB) cross section indicates that a doubly doped drain (DDD) (N+) is likely present where a lightly doped drain (LDD) is designated. This defect leads to a failure mode that is consistent with hot-carrier injection in complementary metal-oxide semiconductor (CMOS) transistors. This paper presents the testability from a fault isolation aspect, shmoo plot characterization, and backside optical techniques to identify its spatial location. A discussion of the results includes why ionizing radiation allowed the defect’s capture and potential implications of using ionizing radiation as a viable failure analysis technique.

Fault Localization of Metal Defects with Si-CCD Camera in Analog Device Functional Failure

2013 ◽  
Author(s):  
Stephane Alves ◽  
Philippe Rousseille ◽  
Thomas Zirilli
Keyword(s):  
Photon Emission ◽  
Fault Localization ◽  
Ccd Camera ◽  
Analog Device ◽  
Functional Failure ◽  
Emission Microscopy

Abstract This paper presents a case study on photon emission from metals and demonstrates the capability of Emission Microscopy Si-CCD camera to detect micro metal bridges on functional failures of Analog devices.

Systematic EFA Approach in Locating Floating Nodes in Analog Mixed Signal Devices

2011 ◽  
Author(s):  
Sagar Karki
Keyword(s):  
Integrated Circuits ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Photon Emission ◽  
Timely Manner ◽  
Critical Step ◽  
Isolation Techniques ◽  
Emission Microscopy ◽  
Digital Circuitry

Abstract With advancements in technology, it is nearly impossible to find the defects in integrated circuits without applying appropriate failure isolation techniques. Failure isolation is a critical step in identifying the physical defect on integrated circuits. This paper addresses the challenges imposed by floating node conditions on both analog and digital circuitry, and a case study for each circuit type is presented. Different approaches along with the challenges involved in isolating each case in a very timely manner are addressed. Finally, the usefulness of global isolation tools, such as PEM (Photon Emission Microscopy), FIB (Focused Ion Beam), and micro-probing, is also discussed.

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