Failure Analysis of Sub-Micron Semiconductor Integrated Circuit Using Backside Photon Emission Microscopy

1999 ◽  
Author(s):  
Soon Lim ◽  
Jian Hua Bi ◽  
Lian Choo Goh ◽  
Soh Ping Neo ◽  
Sudhindra Tatti
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Photon Emission ◽  
Fault Isolation ◽  
Integrated Circuit Fabrication ◽  
Circuit Fabrication ◽  
Emission Microscopy ◽  
On Chip

Abstract The progress of modern day integrated circuit fabrication technology and packaging has made fault isolation using conventional emission microscopy via the top of the integrated circuit more difficult, if not impossible. This is primarily due to the use of increased levels and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution to this problem. This paper outlines the failure analysis of sub-micron silicon integrated circuits using backside photon emission microscopy. Sample preparation, practical difficulties encountered and case histories will be discussed.

Reliable Metallization System for Flip-Chip Optoelectronic Integrated Circuits

1992 ◽  
Vol 260 ◽  
Author(s):  
Osamu Wada
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Optical Receivers ◽  
Integrated Circuit Fabrication ◽  
Aging Test ◽  
Circuit Fabrication ◽  
Reaction Barriers ◽  
Integrated Receivers ◽  
Device Operation

ABSTRACTThermal stability of evaporated Pd, Pt and Rh films as reaction barriers to Au-Sn solder was studied for the application to fl1p-ch1p optoelectronic integration. Sn 1n the solder diffused preferentially Into a barrier metal uniformly to produce more stable IntermetalUc phases for all three metals. Pt and Rh exhibited sufficiently samll 1nterd1ffus1on coefficients with high activation energies 1n the temperature range of device operation (Pt: 1.35 eV, Rh: 1.95 eV). This result demonstartes the usefulness of Pt and Rh 1n practical flip-chip Integrated circuit fabrication. Aging test was conducted on fl1p-ch1p GalnAs/InP p-1-n photodiodes with Au-Sn/Pt metallization and no severe degradation was observed over 3400 h at 180 ° C. The same metallization techniques were applied 1n the fabrication of 10 Gbps optoelectronic Integrated receivers as well as quad p-i-n photodiodes for coherent optical receivers.

Debug and Fault Isolation of an RF/IF Circuit for 3G Cellular Applications With High Leakage: A Case Study

2002 ◽  
Author(s):  
Syd Wilson ◽  
Manoj Nair ◽  
Michael Vicker ◽  
Richard B. Meador ◽  
George Smoot ◽  
...  
Keyword(s):  
Leakage Current ◽  
Integrated Circuit ◽  
Photon Emission ◽  
Cost Effective ◽  
Fault Isolation ◽  
Cellular Phones ◽  
Third Generation ◽  
Mixed Signal ◽  
Emission Microscopy

Abstract First silicon of a cost effective, BICMOS mixed signal RF/IF integrated circuit (IC) for third generation (3G) cellular phones showed high leakage current on the analog receive supply pins in “battery save” mode. Our tasks were to identify and isolate the source of leakage and to fix the design. Alternate debug techniques were used to isolate the cause of the leakage and provide a solution after inconclusive results were obtained using photon emission microscopy,(1) and infrared microthermography techniques.

scholarly journals Die Backside FIB Preparation for Identification and Characterization of Metal Voids

1999 ◽  
Author(s):  
Ann N. Campbell ◽  
William F. Filter ◽  
Nicholas Antoniou
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Cross Sections ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Milling Process ◽  
Plan View ◽  
Metal Interconnects

Abstract Both the increased complexity of integrated circuits, resulting in six or more levels of integration, and the increasing use of flip-chip packaging have driven the development of integrated circuit (IC) failure analysis tools that can be applied to the backside of the chip. Among these new approaches are focused ion beam (FIB) tools and processes for performing chip edits/repairs from the die backside. This paper describes the use of backside FIB for a failure analysis application rather than for chip repair. Specifically, we used FIB technology to prepare an IC for inspection of voided metal interconnects (“lines”) and vias. Conventional FIB milling was combined with a superenhanced gas assisted milling process that uses XeF2 for rapid removal of large volumes of bulk silicon. This combined approach allowed removal of the TiW underlayer from a large number of M1 lines simultaneously, enabling rapid localization and plan view imaging of voids in lines and vias with backscattered electron (BSE) imaging in a scanning electron microscope (SEM). Sequential cross sections of individual voided vias enabled us to develop a 3D reconstruction of these voids. This information clarified how the voids were formed, helping us identify the IC process steps that needed to be changed.

Backside Deprocessing of CMOS SOI Devices for Physical Defect and Failure Analysis

2003 ◽  
Author(s):  
Seth J. Prejean ◽  
Joseph Shannon
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Flip Chip ◽  
Fault Isolation ◽  
Oxide Semiconductor ◽  
Easy Access ◽  
Induced Voltage ◽  
Emission Analysis ◽  
Defect Localization ◽  
Soi Devices

Abstract This paper describes improvements in backside deprocessing of CMOS (Complimentary Metal Oxide Semiconductor) SOI (Silicon On Insulator) integrated circuits. The deprocessing techniques described here have been adapted from a previous research publication on backside deprocessing of bulk CMOS integrated circuits [1]. The focus of these improvements was to provide a repeatable and reliable methodology of deprocessing CMOS devices from the backside. We describe a repeatable and efficient technique to deprocess flip chip packaged devices and unpackaged die from the backside. While this technique has been demonstrated on SOI and bulk devices, this paper will focus on the latest SOI technology. The technique is useful for quick and easy access to the transistor level while preserving the metal interconnects for further analysis. It is also useful for deprocessing already thinned or polished die without removing them from the package. Removing a thin die from a package is very difficult and could potentially damage the device. This is especially beneficial when performing physical failure analysis of samples that have been back thinned for the purpose of fault isolation and defect localization techniques such as: LIVA (Laser Induced Voltage Alteration), TIVA (Thermally Induce Voltage Alteration), SDL [2] (Soft Defect Localization), and TRE (Time Resolved Emission) analysis. An important fundamental advantage of deprocessing SOI devices is that the BOX (Buried Oxide) layer acts as a chemical etch stop when etching the backside or bulk silicon. This leaves the transistor active silicon intact for analysis. Further delayering allows for the inspection of the active silicon, gate oxide, silicide, spacers, and poly. After deprocessing the transistor level, the metal layers are still intact and, in most cases, still electrically connected to the outside world. This can provide additional failure analysis opportunities.

Thermal Failure Analysis of Functional Failures by IR Lock-in Thermal Emission

2019 ◽  
Author(s):  
Paul Hubert P. Llamera ◽  
Camille Joyce G. Garcia-Awitan
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Near Infrared ◽  
Thermal Emission ◽  
Fault Localization ◽  
Fault Isolation ◽  
Distinct Advantage ◽  
Infra Red ◽  
Emission Microscopy ◽  
Lock In

Abstract Lock-in thermography (LIT), known as a powerful nondestructive fault localization technique, can also be used for microscopic failure analysis of integrated circuits (ICs). The dynamic characteristic of LIT in terms of measurement, imaging and sensitivity, is a distinct advantage compared to other thermal fault localization methods as well as other fault isolation techniques like emission microscopy. In this study, LIT is utilized for failure localization of units exhibiting functional failure. Results showed that LIT was able to point defects with emissions in the mid-wave infra-red (MWIR) range that Photo Emission Microscopy (PEM) with near infrared (NIR) to short- wave infra-red (SWIR) detection wavelength sensitivity cannot to detect.

Case Study: Failure Analysis of Functional Shmoo Hole with Laser Voltage Probing

2009 ◽  
Author(s):  
S.H. Lee ◽  
Y.W. Lee ◽  
K.T. Lee ◽  
C.Y. Choi ◽  
H.W. Shin ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Photon Emission ◽  
Operating Voltage ◽  
Process Technology ◽  
Time Resolved ◽  
Voltage Drops ◽  
On Chip ◽  
Metal Layers

Abstract Innovations in semiconductor fabrication processes have driven process shrinks partly to fulfill the need for low power, system-on-chip (SOC) devices. As the process is innovated, it influences the related design debug and failure analysis which have gone through many changes. Historically for signal probing, engineers analyzed signals from metal layers by using e-beam probing methods [1]. But due to the increased number of metal layers and the introduction of flip chip packages, new signal probing systems were developed which used time resolved photon emission (TRE) to measure signals through the backside. However, as the fabrication process technology continues to shrink, the operating voltage drops as well. When the operating voltage drops below 1.0V, signal probing systems using TRE find it harder to detect the signals [2]. Fortunately, Laser Voltage Probing (LVP) technology [3] is capable of probing beyond this limitation of TRE. In this paper, we used an LVP system to analyze and identify a functional shmoo hole failure. We also proposed the design change to prevent its reoccurrence.

Detecting Power Shorts from Front and Backside of IC Packages Using Scanning SQUID Microscopy

1999 ◽  
Author(s):  
L. A. Knauss ◽  
B. M. Frazier ◽  
H. M. Christen ◽  
S. D. Silliman ◽  
K. S. Harshavardhan ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Quantum Interference ◽  
Flip Chip ◽  
Near Field ◽  
Current Density Distribution ◽  
Scanning Squid ◽  
Tools And Techniques ◽  
The Magnetic Field

Abstract As process technologies of integrated circuits become more complex and the industry moves toward flipchip packaging, present tools and techniques are having increasing difficulty in meeting failure analysis needs. One of the most common failures in these types of ICs and packages is power shorts, both during fabrication and in the field. Many techniques such as Emission Microscopy and Liquid Crystal are either not able to locate power shorts or are inhibited in their effectiveness by multiple layers of metal and flip-chip type packaging. A scanning SQUID microscope can overcome some of these difficulties. A SQUID (Superconducting Quantum Interference Device) is a very sensitive magnetic sensor that can image magnetic fields generated by magnetic materials or currents (such as those in an integrated circuit). The current density distribution in the sample can then be calculated from the magnetic field image, and resolutions approaching 5 times the near field limit can be obtained. We present here the application of a SQUID microscope to physical failure analysis and compare it with other techniques to detect shorted current paths in flip-chip mounted ICs and packages.

Analysis of Delta Iddq Soft Fails on Pass Chips

2006 ◽  
Author(s):  
I. Österreicher ◽  
S. Eckl ◽  
B. Tippelt ◽  
S. Döring ◽  
R. Prang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mode ◽  
Photon Emission ◽  
Complete Analysis ◽  
Functional Tests ◽  
Analysis Techniques ◽  
Atomic Force ◽  
Current Consumption ◽  
Emission Microscopy ◽  
Failure Localization

Abstract Depending on the field of application the ICs have to meet requirements that differ strongly from product to product, although they may be manufactured with similar technologies. In this paper a study of a failure mode is presented that occurs on chips which have passed all functional tests. Small differences in current consumption depending on the state of an applied pattern (delta Iddq measurement) are analyzed, although these differences are clearly within the usual specs. The challenge to apply the existing failure analysis techniques to these new fail modes is explained. The complete analysis flow from electrical test and Global Failure Localization to visualization is shown. The failure is localized by means of photon emission microscopy, further analyzed by Atomic Force Probing, and then visualized by SEM and TEM imaging.

Thin-Die Flip Chip Physical-FA Process Flow

2002 ◽  
Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Preparation Methods ◽  
Chip Technology ◽  
Isolation Test ◽  
Sample Preparation Methods

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

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