Enhancing Point Defect Isolation by Using Ionizing Radiation

2019 ◽  
Author(s):  
Douglas J. Martin ◽  
Matthew J. Gadlage ◽  
Wai-Yat Leung ◽  
Jeffrey L. Titus
Keyword(s):  
Ionizing Radiation ◽  
Integrated Circuit ◽  
Focused Ion Beam ◽  
High Reliability ◽  
Ion Beam ◽  
Photon Emission ◽  
Fault Isolation ◽  
Oxide Semiconductor ◽  
Carrier Injection ◽  
Failure Site

Abstract An application-specific integrated circuit (ASIC) for a high reliability application is found to have a missing sidewall spacer in a single transistor. Manufacturer burn-in and standard component electrical tests do not capture this defect. The defect manifests after exposure to ionizing radiation. Photon emission microscopy (PEM), laser voltage imaging (LVI), and laserassisted device alteration (LADA) are used to isolate the failure site. At the failure site a focused ion beam (FIB) cross section indicates that a doubly doped drain (DDD) (N+) is likely present where a lightly doped drain (LDD) is designated. This defect leads to a failure mode that is consistent with hot-carrier injection in complementary metal-oxide semiconductor (CMOS) transistors. This paper presents the testability from a fault isolation aspect, shmoo plot characterization, and backside optical techniques to identify its spatial location. A discussion of the results includes why ionizing radiation allowed the defect’s capture and potential implications of using ionizing radiation as a viable failure analysis technique.

scholarly journals Practical Methodologies in Restoring Initial Failure Mode and Backside Focused Ion Beam Cross-Section for Defect Visualization

2021 ◽  
Author(s):  
Alvina Jean Tampos ◽  
Karl Villareal
Keyword(s):  
Failure Mode ◽  
Cross Section ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Image Sensor ◽  
Fault Isolation ◽  
Third Party ◽  
Oxide Semiconductor ◽  
Back Side

Abstract Complementary Metal-Oxide Semiconductor (CMOS) Image Sensors are gaining popularity most especially in Automotive Safety and Advanced Driver-Assistance Systems (ADAS) applications. Customer application modules involve oftentimes a third party supplier. When failures involve interaction between an image sensor die and the customer's module, the Failure Analyst has to know the exact failure mechanism to pinpoint whether root cause is in the die fabrication (fab) or packaging assembly (third party supplier). Challenges can befall the analyst: failure modes can recover which renders the unit functional and laboratories most often do not have complete sophisticated analytical laboratory equipment for electrical testing, fault isolation and sample preparation. In this paper, a case study of a CMOS Image Sensor is presented wherein the failure mode recovered which was restored and how the structural limitations were overcome for fault isolation on both front- and back-side. A modified process flow was performed to visualize the defect through backside Focused Ion Beam (FIB) cross-section.

scholarly journals Fast and Effective Sample Preparation Technique for Backside Fault Isolation on GaN Packaged Devices

2021 ◽  
Author(s):  
Tony Colpaert ◽  
Stefaan Verleye
Keyword(s):  
Sample Preparation ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Photon Emission ◽  
Fault Isolation ◽  
Preparation Technique ◽  
Laser Marking ◽  
Sample Preparation Technique ◽  
P Type ◽  
Metal Layers

Abstract This paper describes a fast and effective sample preparation method to allow backside fault localization on GaN package devices. Backside analysis by Photon Emission Microscopy (PEM) is becoming preferable to frontside analysis when the die is covered by metal layers. This paper describes an optimized method for backside sample preparation on GaN package devices having a thick heavily doped p-type silicon substrate. The method combines mechanical and chemical deprocessing steps, resulting in a fast and effective sample preparation technique for PEM analysis. Additionally, the laser marking process parameters to facilitate orientation during the final physical failure analysis by Focused Ion Beam (FIB) are also shared.

Failure Analysis on Inter Polysilicon Oxide Reliability Issues of 40nm Automotive NVM Device

2019 ◽  
Author(s):  
P. K. Tan ◽  
R. Fransiscus ◽  
Y. L. Pan ◽  
H. H. W. Thoungh ◽  
S. L. Ting ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Dielectric Breakdown ◽  
Complementary Metal Oxide Semiconductor ◽  
Fault Isolation ◽  
Oxide Semiconductor ◽  
Carrier Injection ◽  
Operating Life ◽  
Tem Analysis ◽  
Root Cause

Abstract Reliability tests, such as Time-Dependent Dielectric Breakdown (TDDB), High-Temperature Operating Life (HTOL), Hot Carrier Injection (HCI), etc., is required for the lifetime prediction of an integrated circuit (IC) product. Those reliability tests are more stringent and complex especially for automotive Complementary Metal–Oxide–Semiconductor (CMOS) devices, this because it involves human lives and safety. In foundries failure analysis (FA), Transmission Electron Microscopy (TEM) analysis often required in order to provide insights into the defect mechanisms and the root cause of the reliability tests. In this paper, application of high resolution Nano-probing Electron Beam Absorbance Current (EBAC), Nano-probing active passive voltage contrast (APVC), and TEM with Energy Dispersive X-Ray Spectroscopy (EDX) to identify the failing root cause of Inter- Poly Oxide (IPO) TDDB failure on an automotive grade Non- Volatile Memory (NVM) device was investigated. We have successfully demonstrated that TEM analysis after Nanoprobing EBAC/APVC fault isolation is an effective technique to reveal the failure root cause of IPO breakdown after reliability stresses.

Novel Approach of Improving Secondary Electron Detector in FIB System

2018 ◽  
Author(s):  
Steve Wang ◽  
Jim McGinn ◽  
Peter Tvarozek ◽  
Amir Weiss
Keyword(s):  
Integrated Circuit ◽  
Secondary Electron ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Vital Role ◽  
Electron Detector ◽  
System A ◽  
Novel Approach

Abstract Secondary electron detector (SED) plays a vital role in a focused ion beam (FIB) system. A successful circuit edit requires a good effective detector. Novel approach is presented in this paper to improve the performance of such a detector, making circuit altering for the most advanced integrated circuit (IC) possible.

Electrical Characterization of Different Failure Modes in Sub-100 nm Devices Using Nanoprobing Technique

2009 ◽  
Author(s):  
E. Hendarto ◽  
S.L. Toh ◽  
J. Sudijono ◽  
P.K. Tan ◽  
H. Tan ◽  
...  
Keyword(s):  
Electron Microscope ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Nickel Silicide ◽  
Fault Isolation ◽  
Technology Nodes ◽  
Scanning Electron

Abstract The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.

TEM Sample Preparation Tricks for Advanced DRAMs

2015 ◽  
Author(s):  
Ching Shan Sung ◽  
Hsiu Ting Lee ◽  
Jian Shing Luo
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Sample Preparation ◽  
Integrated Circuit ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Tem Analysis ◽  
Cross Sectional ◽  
Transmission Electron ◽  
Characterization Of Materials

Abstract Transmission electron microscopy (TEM) plays an important role in the structural analysis and characterization of materials for process evaluation and failure analysis in the integrated circuit (IC) industry as device shrinkage continues. It is well known that a high quality TEM sample is one of the keys which enables to facilitate successful TEM analysis. This paper demonstrates a few examples to show the tricks on positioning, protection deposition, sample dicing, and focused ion beam milling of the TEM sample preparation for advanced DRAMs. The micro-structures of the devices and samples architectures were observed by using cross sectional transmission electron microscopy, scanning electron microscopy, and optical microscopy. Following these tricks can help readers to prepare TEM samples with higher quality and efficiency.

Automatic Determination of Optimal FIB Operations for Improved Circuit Probing and Fast Reconfiguration

2000 ◽  
Author(s):  
Romain Desplats ◽  
Timothee Dargnies ◽  
Jean-Christophe Courrege ◽  
Philippe Perdu ◽  
Jean-Louis Noullet
Keyword(s):  
Integrated Circuit ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Semiconductor Devices ◽  
Front Side ◽  
Automatic Determination ◽  
Metal Line ◽  
New Approach ◽  
Metal Layers

Abstract Focused Ion Beam (FIB) tools are widely used for Integrated Circuit (IC) debug and repair. With the increasing density of recent semiconductor devices, FIB operations are increasingly challenged, requiring access through 4 or more metal layers to reach a metal line of interest. In some cases, accessibility from the front side, through these metal layers, is so limited that backside FIB operations appear to be the most appropriate approach. The questions to be resolved before starting frontside or backside FIB operations on a device are: 1. Is it do-able, are the metal lines accessible? 2. What is the optimal positioning (e.g. accessing a metal 2 line is much faster and easier than digging down to a metal 6 line)? (for the backside) 3. What risk, time and cost are involved in FIB operations? In this paper, we will present a new approach, which allows the FIB user or designer to calculate the optimal FIB operation for debug and IC repair. It automatically selects the fastest and easiest milling and deposition FIB operations.

A Methodology to Reduce Ion Beam Induced Damage in TEM Specimens Prepared by FIB

2002 ◽  
Author(s):  
Chin Kai Liu ◽  
Chi Jen. Chen ◽  
Jeh Yan.Chiou ◽  
David Su
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Sample Preparation ◽  
Integrated Circuit ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Specimen Preparation ◽  
Tem Analysis ◽  
Sensitive Issue ◽  
Transmission Electron

Abstract Focused ion beam (FIB) has become a useful tool in the Integrated Circuit (IC) industry, It is playing an important role in Failure Analysis (FA), circuit repair and Transmission Electron Microscopy (TEM) specimen preparation. In particular, preparation of TEM samples using FIB has become popular within the last ten years [1]; the progress in this field is well documented. Given the usefulness of FIB, “Artifact” however is a very sensitive issue in TEM inspections. The ability to identify those artifacts in TEM analysis is an important as to understanding the significance of pictures In this paper, we will describe how to measure the damages introduced by FIB sample preparation and introduce a better way to prevent such kind of artifacts.

Integrated Circuit Device Repair Using FIB System: Tips, Tricks, and Strategies

1999 ◽  
Author(s):  
K. N. Hooghan ◽  
K. S. Wills ◽  
P.A. Rodriguez ◽  
S.J. O’Connell
Keyword(s):  
Integrated Circuit ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Dead Reckoning ◽  
Physical Damage ◽  
Art Form ◽  
Metal Levels ◽  
Potential Damage ◽  
On Chip ◽  
Beam Currents

Abstract Device repair using Focused Ion Beam(FIB) systems has been in use for most of the last decade. Most of this has been done by people who have been essentially self-taught. The result has been a long learning curve to become proficient in device repair. Since a great deal of the problem is that documentation on this “art form” is found in papers from many different disciplines, this work attempts to summarize all of the available information under one title. The primary focus of FIB device repair is to ensure and maintain device integrity and subsequently retain market share while optimizing the use of the instrument, usually referred to as ‘beam time’. We describe and discuss several methods of optimizing beam time. First, beam time should be minimized while doing on chip navigation to reach the target areas. Several different approaches are discussed: dead reckoning, 3-point alignment, CAD-based navigation, and optical overlay. Second, after the repair areas are located and identified, the desired metal levels must be reached using a combination of beam currents and gas chemistries, and then filled up and strapped to make final connections. Third, cuts and cleanups must be performed as required for the final repair. We will discuss typical values of the beam currents required to maintain device integrity while concurrently optimizing repair time. Maintaining device integrity is difficult because of two potentially serious interactions of the FIB on the substrate: 1) since the beam consists of heavy metal ions (typically Gallium) the act of imaging the surface produces some physical damage; 2) the beam is positively charged and puts some charge into the substrate, making it necessary to use great care working in and around capacitors or active areas such as transistors, in order to avoid changing the threshold voltage of the devices. Strategies for minimizing potential damage and maximizing quality and throughput will be discussed.

scholarly journals Three-Dimensional Nanoscale Mapping of State-of-the-Art Field-Effect Transistors (FinFETs)

2017 ◽  
Vol 23 (5) ◽  
pp. 916-925
Author(s):  
Pritesh Parikh ◽  
Corey Senowitz ◽  
Don Lyons ◽  
Isabelle Martin ◽  
Ty J. Prosa ◽  
...  
Keyword(s):  
Field Effect ◽  
Focused Ion Beam ◽  
Field Effect Transistors ◽  
Ion Beam ◽  
Semiconductor Industry ◽  
Three Dimensional ◽  
Atom Probe ◽  
Physical Structure ◽  
Oxide Semiconductor ◽  
Device Performance

AbstractThe semiconductor industry has seen tremendous progress over the last few decades with continuous reduction in transistor size to improve device performance. Miniaturization of devices has led to changes in the dopants and dielectric layers incorporated. As the gradual shift from two-dimensional metal-oxide semiconductor field-effect transistor to three-dimensional (3D) field-effect transistors (finFETs) occurred, it has become imperative to understand compositional variability with nanoscale spatial resolution. Compositional changes can affect device performance primarily through fluctuations in threshold voltage and channel current density. Traditional techniques such as scanning electron microscope and focused ion beam no longer provide the required resolution to probe the physical structure and chemical composition of individual fins. Hence advanced multimodal characterization approaches are required to better understand electronic devices. Herein, we report the study of 14 nm commercial finFETs using atom probe tomography (APT) and scanning transmission electron microscopy–energy-dispersive X-ray spectroscopy (STEM-EDS). Complimentary compositional maps were obtained using both techniques with analysis of the gate dielectrics and silicon fin. APT additionally provided 3D information and allowed analysis of the distribution of low atomic number dopant elements (e.g., boron), which are elusive when using STEM-EDS.

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