Backside Sample Preparation Challenges for Fault Localization Analysis of Flip Chip Package

2013 ◽  
Author(s):  
Lihong Cao ◽  
Donna Wallace ◽  
Lynda Tuttle ◽  
Kirk Martin
Keyword(s):  
Image Quality ◽  
Flip Chip ◽  
Thermal Emission ◽  
Photon Emission ◽  
Fault Isolation ◽  
Isolation Techniques ◽  
High Uniformity ◽  
Localization Analysis ◽  
Mechanical Thinning ◽  
The Impact

Abstract Mechanical thinning of Si die backside was introduced to support fault isolation for flip chip package in this paper. The backside milling system provides two types of thinning with good die planarity and mirror polishing to yield a high image quality for fault isolation techniques such as laser base thermal emission and photon emission techniques. In this paper, two mechanical thinning techniques were applied by using the 3D die curvature thinning and 2D planar thinning on flip chip Si backside. The impact of process parameters on die planarity and fault isolation were also discussed. The experimental results demonstrate the milling system’s high uniformity across the large die size and provide a very good solution for fault isolation techniques.

Advanced Non-Destructive Fault Isolation Techniques for PCB Substrates Using Magnetic Current Imaging and Terahertz Time Domain Reflectometry

2018 ◽  
Author(s):  
Daechul Choi ◽  
Yoonseong Kim ◽  
Jongyun Kim ◽  
Han Kim
Keyword(s):  
Time Domain ◽  
Quantum Interference ◽  
Flip Chip ◽  
Imaging System ◽  
Time Domain Reflectometry ◽  
Fault Isolation ◽  
Magnetic Current ◽  
Isolation Techniques ◽  
Super Conducting ◽  
Non Destructive

Abstract In this paper, we demonstrate cases for actual short and open failures in FCB (Flip Chip Bonding) substrates by using novel non-destructive techniques, known as SSM (Scanning Super-conducting Quantum Interference Device Microscopy) and Terahertz TDR (Time Domain Reflectometry) which is able to pinpoint failure locations. In addition, the defect location and accuracy is verified by a NIR (Near Infra-red) imaging system which is also one of the commonly used non-destructive failure analysis tools, and good agreement was made.

Magnetic Current Imaging Power Short Localization

2015 ◽  
Author(s):  
J. Gaudestad ◽  
F. Rusli ◽  
A. Orozco ◽  
M.C. Pun
Keyword(s):  
Thermal Imaging ◽  
Flip Chip ◽  
Optical Microscope ◽  
Fault Isolation ◽  
Magnetic Current ◽  
Multiple Fault ◽  
Defect Location ◽  
Isolation Techniques ◽  
Chip Sample

Abstract A Flip Chip sample failed short between power and ground. The reference unit had 418Ω and the failed unit with the short had 16.4Ω. Multiple fault isolation techniques were used in an attempt to find the failure with thermal imaging and Magnetic Current Imaging being the only techniques capable of localizing the defect. To physically verify the defect location, the die was detached from the substrate and a die cracked was seen using a visible optical microscope.

Debugging Phase-Locked Loop Failures in Integrated Circuit Products

2014 ◽  
Author(s):  
S.H. Goh ◽  
Wendy Lau ◽  
B.L. Yeoh ◽  
H.W. Ho ◽  
G.F. You ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Frequency Control ◽  
Photon Emission ◽  
Building Blocks ◽  
Phase Locked Loop ◽  
Fault Isolation ◽  
Loop Control ◽  
Isolation Techniques ◽  
Loop Control System ◽  
Specific Frequency

Abstract A phase-locked loop (PLL) is commonly used in integrated circuit devices for frequency control. In a finished product, it comprises of sub-building blocks operating in a closed-loop control system which do not have register readback or test access points for easy debugging. Failure analysis becomes a challenge. This paper demonstrates the inherent limitation of relying only on dynamic fault isolation techniques, in specific frequency mapping for PLL failure debug. A systematic debug approach that combines volume failure characterization on test, additional characterization using dynamic photon emission and design simulation is then presented. Results are obtained on a 28 nm node device.

LTCC-Based Highly Integrated SiPM Module with Integrated Liquid Cooling Channels for High Resolution Molecular Imaging

2018 ◽  
Vol 15 (2) ◽  
pp. 86-94 ◽  
Author(s):  
Rainer Dohle ◽  
Ilaria Sacco ◽  
Thomas Rittweg ◽  
Thomas Friedrich ◽  
Gerold Henning ◽  
...  
Keyword(s):  
Magnetic Resonance ◽  
Image Quality ◽  
Low Temperature ◽  
Flip Chip ◽  
Back Side ◽  
Liquid Cooling ◽  
Cooling Channels ◽  
Hybrid Detection ◽  
The Impact ◽  
Ltcc Substrate

We present a very compact hybrid detection module based on an advanced liquid-cooled low temperature cofired ceramic (LTCC) substrate. The double sided hybrid combines 144 photo detectors and four specialized flip chip readout ASICs (Application specific Integrated Circuits) used for the readout of scintillation crystals with application in time-of-flight positron emission tomography (PET) combined with magnetic resonance imaging (MRI). If MRI images and PET images are combined, completely new medical diagnostic and treatment prospects are feasible because the two techniques are complementary and they will offer both anatomical and functional information. One of the biggest challenges is the development of miniaturized detector modules that are highly functional and MRI compatible. Our SiPM (Silicon Photomultiplier) module has an area of 32.8 by 32.0 mm2 and contains 12 × 12 SiPMs in a pitch of 2.5 mm2. The SiPM readout of the 144 channels is performed by four PETA6 ASICs. The LTCC substrate with a 2.1 mm thickness has been manufactured using the most advanced technologies developed at Micro Systems Engineering GmbH To guarantee the manufacturability in serial or mass production, DP951 P2 green tape has been used. For the cooling channels, special technology has been developed by MSE. The liquid cooling channels inside the LTCC substrate provide excellent cooling for the ASICs, the SiPMs, and thermal insulation between ASICs and SiPMs and allow a very compact design of the detector modules, reducing their height by 50% compared with other technical solutions. We can insert a ring of our modules in an existing MR (Magnetic Resonance) scanner. Operating the SiPMs at low temperature improves their performance, reducing the effects of dark count rate and improving image quality. There is no heatsink, heat pipe, or other cooling element attached to the back side of the ASICs. To avoid interference between the PET and MRI system, short signal length is required for minimizing pickup loops and eddy currents. The 12 SiPM arrays with 2 × 6 geometry are wire bonded only at the edges of the SiPMs to the LTCC, enabling the use of nearly the whole detector area for photon detection, which is of paramount importance for excellent image quality. At the opposite side of the substrate, four ASICs with 272 μm bump pitch are flip chip solder assembled to the LTCC substrate including underfilling, and a few SMD (Surface Mount Device) components are mounted. A scintillator crystal array on top of the SiPMs converts gamma rays (511 keV photons produced from positron-electron annihilation) into light. We assume that the LTCC substrates and all components are fully MRI compatible, which is important for the integration of PET with MRI without mutual interference. The paper elucidates the impact of the used technology on the performance of advanced PET/MRI detector modules.

Combining Volume Scan Diagnosis and Dynamic Failure Analysis for Precise Isolation of Manufacturing Defects

2017 ◽  
Author(s):  
A.M. Jakati ◽  
R. Deshpande ◽  
K.A. Serrels ◽  
P. Babighian ◽  
G. Dabney ◽  
...  
Keyword(s):  
Semiconductor Manufacturing ◽  
Photon Emission ◽  
Fault Isolation ◽  
Manufacturing Defects ◽  
Voltage Imaging ◽  
Isolation Techniques ◽  
Advanced Technologies ◽  
Manufacturing Technologies ◽  
Non Destructive ◽  
Random Particle

Abstract Advances in semiconductor manufacturing technologies have led to newer types of defects that are difficult to identify, causing longer yield ramp times. Traditionally, yield has been limited to random particle defects but layout systematic defects are increasingly dominating the fail paretos on advanced technologies. Identifying systematic defects precisely and rapidly is a must. This paper codifies a methodology that combines volume scan diagnosis and non-destructive electrical fault isolation techniques such as photon-emission microscopy, soft defect localization and laser voltage imaging/probing to debug manufacturing defects precisely.

Failure Analysis of Sub-Micron Semiconductor Integrated Circuit Using Backside Photon Emission Microscopy

1999 ◽  
Author(s):  
Soon Lim ◽  
Jian Hua Bi ◽  
Lian Choo Goh ◽  
Soh Ping Neo ◽  
Sudhindra Tatti
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Photon Emission ◽  
Fault Isolation ◽  
Integrated Circuit Fabrication ◽  
Circuit Fabrication ◽  
Emission Microscopy ◽  
On Chip

Abstract The progress of modern day integrated circuit fabrication technology and packaging has made fault isolation using conventional emission microscopy via the top of the integrated circuit more difficult, if not impossible. This is primarily due to the use of increased levels and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution to this problem. This paper outlines the failure analysis of sub-micron silicon integrated circuits using backside photon emission microscopy. Sample preparation, practical difficulties encountered and case histories will be discussed.

Comparison of Photon and Thermal Emission Microscopy for Dynamic Fault Isolation

2015 ◽  
Author(s):  
S.H. Goh ◽  
G.F. You ◽  
Alan Tan ◽  
C.V. Bharadwaj ◽  
Hu Hao ◽  
...  
Keyword(s):  
Thermal Emission ◽  
Photon Emission ◽  
Fault Localization ◽  
Optical Resolution ◽  
Fault Isolation ◽  
Thermal Microscopy ◽  
Emission Microscopy

Abstract Unlike photon emission microscopy which is usually the first go-to technique in tester-based or dynamic electrical fault localization, infrared thermal microscopy does not play a similar routine role despite its comparable ease in application. While thermal emission lacks in optical resolution, we demonstrate superior sensitivity and accuracy over photon emission on dynamic fault localization of backend-of-line short defects.

Thin-Die Flip Chip Physical-FA Process Flow

2002 ◽  
Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Preparation Methods ◽  
Chip Technology ◽  
Isolation Test ◽  
Sample Preparation Methods

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

Extending Acoustic Microscopy for Comprehensive Failure Analysis Applications

2010 ◽  
Author(s):  
Sebastian Brand ◽  
Matthias Petzold ◽  
Peter Czurratis ◽  
Peter Hoffrogge
Keyword(s):  
Image Processing ◽  
Failure Analysis ◽  
Signal Analysis ◽  
Flip Chip ◽  
Fault Isolation ◽  
Acoustic Microscopy ◽  
Specific Information ◽  
Full Potential ◽  
Time Frequency ◽  
Non Destructive

Abstract In industrial manufacturing of microelectronic components, non-destructive failure analysis methods are required for either quality control or for providing a rapid fault isolation and defect localization prior to detailed investigations requiring target preparation. Scanning acoustic microscopy (SAM) is a powerful tool enabling the inspection of internal structures in optically opaque materials non-destructively. In addition, depth specific information can be employed for two- and three-dimensional internal imaging without the need of time consuming tomographic scan procedures. The resolution achievable by acoustic microscopy is depending on parameters of both the test equipment and the sample under investigation. However, if applying acoustic microscopy for pure intensity imaging most of its potential remains unused. The aim of the current work was the development of a comprehensive analysis toolbox for extending the application of SAM by employing its full potential. Thus, typical case examples representing different fields of application were considered ranging from high density interconnect flip-chip devices over wafer-bonded components to solder tape connectors of a photovoltaic (PV) solar panel. The progress achieved during this work can be split into three categories: Signal Analysis and Parametric Imaging (SA-PI), Signal Analysis and Defect Evaluation (SA-DE) and Image Processing and Resolution Enhancement (IP-RE). Data acquisition was performed using a commercially available scanning acoustic microscope equipped with several ultrasonic transducers covering the frequency range from 15 MHz to 175 MHz. The acoustic data recorded were subjected to sophisticated algorithms operating in time-, frequency- and spatial domain for performing signal- and image analysis. In all three of the presented applications acoustic microscopy combined with signal- and image processing algorithms proved to be a powerful tool for non-destructive inspection.

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

2010 ◽  
Author(s):  
Sarven Ipek ◽  
David Grosjean
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Analysis Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

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