Combining Volume Scan Diagnosis and Dynamic Failure Analysis for Precise Isolation of Manufacturing Defects

2017 ◽  
Author(s):  
A.M. Jakati ◽  
R. Deshpande ◽  
K.A. Serrels ◽  
P. Babighian ◽  
G. Dabney ◽  
...  
Keyword(s):  
Semiconductor Manufacturing ◽  
Photon Emission ◽  
Fault Isolation ◽  
Manufacturing Defects ◽  
Voltage Imaging ◽  
Isolation Techniques ◽  
Advanced Technologies ◽  
Manufacturing Technologies ◽  
Non Destructive ◽  
Random Particle

Abstract Advances in semiconductor manufacturing technologies have led to newer types of defects that are difficult to identify, causing longer yield ramp times. Traditionally, yield has been limited to random particle defects but layout systematic defects are increasingly dominating the fail paretos on advanced technologies. Identifying systematic defects precisely and rapidly is a must. This paper codifies a methodology that combines volume scan diagnosis and non-destructive electrical fault isolation techniques such as photon-emission microscopy, soft defect localization and laser voltage imaging/probing to debug manufacturing defects precisely.

Advantage of AFP Nanoprobing on the 28 nm Technology Failure Analysis

2013 ◽  
Author(s):  
C.Q. Chen ◽  
G.B. Ang ◽  
S.P. Zhao ◽  
Q. Alfred ◽  
N. Dayanand ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Semiconductor Manufacturing ◽  
Fault Isolation ◽  
Feature Size ◽  
Device Characterization ◽  
Advanced Technologies ◽  
Afm Imaging ◽  
Imaging Mode ◽  
Manufacturing Technologies ◽  
Level Analysis

Abstract As the rapid developments of semiconductor manufacturing technologies, the CD of the device keep shrinking. The IC devices have a smaller feature sizes and higher densities, and thus there are many challenges come up in terms of the failure analysis and localized device characterization. Besides the challenge of smaller feature size, there is another challenge as well. Some of the traditional FA method can no longer be employed on advanced technologies, such as 28nm and beyond. Quickly and successfully isolating the failed location and obtaining electrical signature of the defect has become more of a challenge, especially for the device level analysis and characterization. AFP nanoprobing system provides some solutions to advanced nodes fault isolation through its AFM imaging mode of CAFM.

Advanced Non-Destructive Fault Isolation Techniques for PCB Substrates Using Magnetic Current Imaging and Terahertz Time Domain Reflectometry

2018 ◽  
Author(s):  
Daechul Choi ◽  
Yoonseong Kim ◽  
Jongyun Kim ◽  
Han Kim
Keyword(s):  
Time Domain ◽  
Quantum Interference ◽  
Flip Chip ◽  
Imaging System ◽  
Time Domain Reflectometry ◽  
Fault Isolation ◽  
Magnetic Current ◽  
Isolation Techniques ◽  
Super Conducting ◽  
Non Destructive

Abstract In this paper, we demonstrate cases for actual short and open failures in FCB (Flip Chip Bonding) substrates by using novel non-destructive techniques, known as SSM (Scanning Super-conducting Quantum Interference Device Microscopy) and Terahertz TDR (Time Domain Reflectometry) which is able to pinpoint failure locations. In addition, the defect location and accuracy is verified by a NIR (Near Infra-red) imaging system which is also one of the commonly used non-destructive failure analysis tools, and good agreement was made.

Debugging Phase-Locked Loop Failures in Integrated Circuit Products

2014 ◽  
Author(s):  
S.H. Goh ◽  
Wendy Lau ◽  
B.L. Yeoh ◽  
H.W. Ho ◽  
G.F. You ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Frequency Control ◽  
Photon Emission ◽  
Building Blocks ◽  
Phase Locked Loop ◽  
Fault Isolation ◽  
Loop Control ◽  
Isolation Techniques ◽  
Loop Control System ◽  
Specific Frequency

Abstract A phase-locked loop (PLL) is commonly used in integrated circuit devices for frequency control. In a finished product, it comprises of sub-building blocks operating in a closed-loop control system which do not have register readback or test access points for easy debugging. Failure analysis becomes a challenge. This paper demonstrates the inherent limitation of relying only on dynamic fault isolation techniques, in specific frequency mapping for PLL failure debug. A systematic debug approach that combines volume failure characterization on test, additional characterization using dynamic photon emission and design simulation is then presented. Results are obtained on a 28 nm node device.

MBIST Driven SRAM Failure Analysis Using Laser Voltage Imaging and Laser Voltage Probing

2019 ◽  
Author(s):  
Jessica Yang ◽  
Omprakash Rengaraj ◽  
Puneet Gupta ◽  
Rudolf Schlangen
Keyword(s):  
Failure Analysis ◽  
Photon Emission ◽  
Random Access ◽  
Random Access Memory ◽  
Fault Isolation ◽  
Static Random Access Memory ◽  
Production Testing ◽  
Access Memory ◽  
Electrical Failure ◽  
Voltage Imaging

Abstract Static Random-Access Memory (SRAM) failure analysis (FA) is important during chip-level reliability evaluation and yield improvement. Single-bit, paired-bit, and quad-bit failures—whose defect should be at the failing bit-cell locations—can be directly sent for Physical Failure Analysis (PFA). For one or multiple row/column failures with too large of a suspected circuit area, more detailed fault isolation is required before PFA. Currently, Photon Emission Microscopy (PEM) is the most commonly used Electrical Failure Analysis (EFA) technique for this kind of fail [1]. Soft-Defect Localization / Dynamic Laser Stimulation (SDL/DLS) can also be applied on soft (Vmin) row/column fails for further isolation [2]. However, some failures do not have abnormal emission spots or DLS sensitivity and require different localization techniques. Laser Voltage Imaging (LVI) and Laser Voltage Probing (LVP) are widely established for logic EFA, [3] but require periodic activation via ATE which may not be possible using MBIST hardware and test-patterns optimized for fast production testing. This paper discusses the test setup challenges to enable LVI & LVP on SRAM fails and includes two case studies on <14 nm advanced process silicon.

Backside Sample Preparation Challenges for Fault Localization Analysis of Flip Chip Package

2013 ◽  
Author(s):  
Lihong Cao ◽  
Donna Wallace ◽  
Lynda Tuttle ◽  
Kirk Martin
Keyword(s):  
Image Quality ◽  
Flip Chip ◽  
Thermal Emission ◽  
Photon Emission ◽  
Fault Isolation ◽  
Isolation Techniques ◽  
High Uniformity ◽  
Localization Analysis ◽  
Mechanical Thinning ◽  
The Impact

Abstract Mechanical thinning of Si die backside was introduced to support fault isolation for flip chip package in this paper. The backside milling system provides two types of thinning with good die planarity and mirror polishing to yield a high image quality for fault isolation techniques such as laser base thermal emission and photon emission techniques. In this paper, two mechanical thinning techniques were applied by using the 3D die curvature thinning and 2D planar thinning on flip chip Si backside. The impact of process parameters on die planarity and fault isolation were also discussed. The experimental results demonstrate the milling system’s high uniformity across the large die size and provide a very good solution for fault isolation techniques.

Verification of DLS Data by LVP in Case of Marginal Failure

2016 ◽  
Author(s):  
Keonil Kim ◽  
Sungjin Kim ◽  
Kunjae Lee ◽  
Kyeongju Jin ◽  
Yunwoo Lee ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Fault Location ◽  
Photon Emission ◽  
Fault Localization ◽  
Fault Isolation ◽  
The Real ◽  
Defect Isolation ◽  
The Relationship ◽  
Non Destructive

Abstract In most of the non-destructive electrical fault isolation cases, techniques such as DLS, Photon Emission, LIT, OBIRCH indicate a fault location directly. But relying on just one of these techniques for marginal failure mechanism is not enough for better fault localization. When Failure Analysis (FA) engineers encounter high NDF (No Defect Found) rates, by using only one of the techniques, they may need to consider the relationship between the responded locations by different techniques and fail phenomenon for better defect isolation. This paper talks about how a responded DLS location does not always indicate a fault location and how LVP data collected using DLS location can pin point the real defect location.

Isolating an Open in 2.5D µBump & Chip Bump Chains using SDR, EBAC and Capacitive Measurements

2019 ◽  
Author(s):  
Kevin Distelhurst ◽  
Doug Hunt ◽  
Dan Bader
Keyword(s):  
Case Studies ◽  
Region Of Interest ◽  
Fault Isolation ◽  
Common Solution ◽  
Root Cause ◽  
Isolation Techniques ◽  
Magnetic Field Imaging ◽  
Semiconductor Packages ◽  
Time Critical ◽  
Non Destructive

Abstract The limitations of Moore’s Law have led to alternatives in semiconductor packages that provide more functionality. Stacking multiple chips in 2.5D and 3D configurations has become a common solution. During the development of these technologies, test chains of chip to chip micro bumps and thru silicon via’s (TSV’s) at various regions within the stack are often employed. These present new challenges to the already difficult process of localizing open and resistive chain fails deep within the stack for root-cause analysis. A combination of quick and effective fault isolation techniques is often required to reliably isolate an open in a time critical situation. Capacitive measurements is a useful technique in some cases for obtaining a quick general location of an open. Magnetic Field Imaging (MFI), specifically Space Domain Reflectometry (SDR), is a non-destructive technique that can provide a relatively accurate location of an open. Electron Beam Absorbed Current (EBAC) is another useful technique in confirming and further isolating the open as the region of interest of the sample is approached via cross-sectioning or planar deprocessing. Case studies using these three techniques are presented and their strengths and weaknesses are discussed. The case studies focus on ìbump and chip bump chains in 2.5D samples.

Dynamic Infrared System Level Fault Isolation

2003 ◽  
Author(s):  
John A. Naoum ◽  
Johan Rahardjo ◽  
Yitages Taffese ◽  
Marie Chagny ◽  
Jeff Birdsley ◽  
...  
Keyword(s):  
Fault Isolation ◽  
System Level ◽  
System Component ◽  
Component Level ◽  
Ir Imaging ◽  
Non Destructive

Abstract The use of Dynamic Infrared (IR) Imaging is presented as a novel, valuable and non-destructive approach for the analysis and isolation of failures at a system/component level.

Fault Localization of Power-Ground Short via Signal Injection and Oscilloscope Technique

2010 ◽  
Author(s):  
Binh Nguyen
Keyword(s):  
Low Cost ◽  
Short Circuit ◽  
Fault Localization ◽  
Fault Isolation ◽  
Test Apparatus ◽  
Good Working ◽  
Signal Injection ◽  
Set Up ◽  
Non Destructive ◽  
Short Circuit Condition

Abstract For those attempting fault isolation on computer motherboard power-ground short issues, the optimal technique should utilize existing test equipment available in the debug facility, requiring no specialty equipment as well as needing a minimum of training to use effectively. The test apparatus should be both easy to set up and easy to use. This article describes the signal injection and oscilloscope technique which meets the above requirements. The signal injection and oscilloscope technique is based on the application of Ohm's law in a short-circuit condition. Two experiments were conducted to prove the effectiveness of these techniques. Both experiments simulate a short-circuit condition on the VCC3 power rail of a good working PC motherboard and then apply the signal injection and oscilloscope technique to localize the short. The technique described is a simple, low cost and non-destructive method that helps to find the location of the power-ground short quickly and effectively.

Extending Acoustic Microscopy for Comprehensive Failure Analysis Applications

2010 ◽  
Author(s):  
Sebastian Brand ◽  
Matthias Petzold ◽  
Peter Czurratis ◽  
Peter Hoffrogge
Keyword(s):  
Image Processing ◽  
Failure Analysis ◽  
Signal Analysis ◽  
Flip Chip ◽  
Fault Isolation ◽  
Acoustic Microscopy ◽  
Specific Information ◽  
Full Potential ◽  
Time Frequency ◽  
Non Destructive

Abstract In industrial manufacturing of microelectronic components, non-destructive failure analysis methods are required for either quality control or for providing a rapid fault isolation and defect localization prior to detailed investigations requiring target preparation. Scanning acoustic microscopy (SAM) is a powerful tool enabling the inspection of internal structures in optically opaque materials non-destructively. In addition, depth specific information can be employed for two- and three-dimensional internal imaging without the need of time consuming tomographic scan procedures. The resolution achievable by acoustic microscopy is depending on parameters of both the test equipment and the sample under investigation. However, if applying acoustic microscopy for pure intensity imaging most of its potential remains unused. The aim of the current work was the development of a comprehensive analysis toolbox for extending the application of SAM by employing its full potential. Thus, typical case examples representing different fields of application were considered ranging from high density interconnect flip-chip devices over wafer-bonded components to solder tape connectors of a photovoltaic (PV) solar panel. The progress achieved during this work can be split into three categories: Signal Analysis and Parametric Imaging (SA-PI), Signal Analysis and Defect Evaluation (SA-DE) and Image Processing and Resolution Enhancement (IP-RE). Data acquisition was performed using a commercially available scanning acoustic microscope equipped with several ultrasonic transducers covering the frequency range from 15 MHz to 175 MHz. The acoustic data recorded were subjected to sophisticated algorithms operating in time-, frequency- and spatial domain for performing signal- and image analysis. In all three of the presented applications acoustic microscopy combined with signal- and image processing algorithms proved to be a powerful tool for non-destructive inspection.

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