Statistical Evaluation of Scan Test Diagnosis Results for Yield Enhancement of Logic Designs

2005 ◽  
Author(s):  
Christian Burmer ◽  
Hans-Peter Erb ◽  
Andreas LemMger ◽  
Markus Gruetzner ◽  
Thomas Schwemboeck ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Statistical Approach ◽  
Test Pattern ◽  
Statistical Evaluation ◽  
Standard Test ◽  
Pattern Generation ◽  
Yield Enhancement ◽  
Diagnostic Features ◽  
Analysis Strategies ◽  
Set Up

Abstract During yield ramp, quick turnaround times between production failures and the results of physical failure analysis are essential. In spite of the growing complexity of today's logic designs, a fast defect localization can be done by using diagnostic features implemented within standard test pattern generation tools. The diagnosis result can not only be used for fault localization but also for statistical analysis based on a large number of failing chips. This statistical approach enables the search for systematic yield detractors and leads to a faster product or technology ramp. This paper describes the necessary steps in order to set up statistical scan diagnosis, discusses the main failure analysis strategies and gives experimental results.

Enabling Electro-Optical Failure Analysis within Extreme Compression Test Architecture

2016 ◽  
Author(s):  
Rudolf Schlangen ◽  
Jon Colburn ◽  
Joe Sarmiento ◽  
Bala Tarun Nelapatla ◽  
Puneet Gupta
Keyword(s):  
Failure Analysis ◽  
Compression Test ◽  
Test Pattern ◽  
Pattern Generation ◽  
Output Data ◽  
Test Compression ◽  
Test Loop ◽  
On Chip ◽  
Test Architecture

Abstract Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.

Volume Electrical Failure Analysis for Product-Specific Yield Enhancement

2010 ◽  
Author(s):  
Steven Kasapi ◽  
Joy Liao ◽  
Bruce Cory ◽  
Izak Kapilevich ◽  
Richard Portune ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Test Pattern ◽  
New Technology ◽  
Significant Benefit ◽  
Yield Enhancement ◽  
Specific Yield ◽  
Design Knowledge ◽  
Electrical Failure ◽  
Defect Localization ◽  
Technology Nodes

Abstract Yield on specific designs often falls far short of predicted yield, especially at new technology nodes. Product-specific yield ramp is particularly challenging because the defects are, by definition, specific to the design, and often require some degree of design knowledge to isolate the failure. Despite the wide variety of advanced electrical failure analysis (EFA) techniques available today, they are not routinely applied during yield ramp. EFA techniques typically require a significant amount of test pattern customization, fixturing modification, or design knowledge. Unless the problem is critical, there is usually not time to apply advanced EFA techniques during yield ramp, despite the potential of EFA to provide valuable defect insight. We present a volume-oriented workflow integrating a limited set of electrical failure analysis (EFA) techniques. We believe this workflow will provide significant benefit by improving defect localization and identification beyond what is available using test-based techniques.

Fault Localization of a Scan Shift Problem on Integrated Logic Designs

2003 ◽  
Author(s):  
C. Burmer ◽  
P. Egger ◽  
A. Huber ◽  
H. Cerva ◽  
D. Petit ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Test Pattern ◽  
Pattern Generation ◽  
Automatic Test Pattern Generation ◽  
Functional Tests ◽  
Scan Design ◽  
Root Cause ◽  
Full Scan ◽  
Integrated Logic

Abstract Effort and complexity for failure analysis are increasing on state of the art logic designs. As chips become more and more complex, functional tests are not possible anymore [1] and are replaced with automatic test pattern generation (ATPG) using a full scan design approach. Analysis of failing devices, however, becomes more complex as scan chains contain a large number of flip flops and localization of the failing net is a prerequisite for subsequent physical failure analysis (PFA). This becomes especially true for flip chip products, since access to the chip front side is not easily possible any more. This report describes the necessary failure analysis steps in order to identify the root cause of scan shift problems associated with two products fabricated in deep sub-micron technology

Test pattern generation for logic crosstalk faults in VLSI circuits

1991 ◽  
Vol 138 (2) ◽  
pp. 179 ◽  
Author(s):  
A. Rubio ◽  
J.A. Sainz ◽  
K. Kinoshita
Keyword(s):  
Test Pattern ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Test Pattern Generation

ATE Failure Isolation Methodologies for Failure Analysis, Design Debug and Yield Enhancement

1998 ◽  
Author(s):  
D.S. Patrick ◽  
L.C. Wagner ◽  
P.T. Nguyen
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Yield Enhancement ◽  
Production Test ◽  
Final Test ◽  
Critical Design ◽  
The Past ◽  
Product Engineering ◽  
Time Savings ◽  
Analysis Design

Abstract Failure isolation and debug of CMOS integrated circuits over the past several years has become increasingly difficult to perform on standard failure analysis functional testers. Due to the increase in pin counts, clock speeds, increased complexity and the large number of power supply pins on current ICS, smaller and less equipped testers are often unable to test these newer devices. To reduce the time of analysis and improve the failure isolation capabilities for failing ICS, failure isolation is now performed using the same production testers used in product development, multiprobe and final test. With these production testers, the test hardware, program and pattern sets are already available and ready for use. By using a special interface that docks the production test head to failure isolation equipment such as the emission microscope, liquid crystal station and E-Beam prober, the analyst can quickly and easily isolate the faillure on an IC. This also enables engineers in design, product engineering and the waferfab yield enhancement groups to utilize this equipment to quickly solve critical design and yield issues. Significant cycle time savings have been achieved with the migration to this method of electrical stimulation for failure isolation.

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

2010 ◽  
Author(s):  
Sarven Ipek ◽  
David Grosjean
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Analysis Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

Failure Analysis of Killer Defects and Yield Enhancement of Flat ROM Devices in Wafer Fabrication

2000 ◽  
Author(s):  
Y. N. Hua ◽  
Z. R. Guo ◽  
L. H. An ◽  
Shailesh Redkar
Keyword(s):  
Electron Microscope ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Wafer Fabrication ◽  
X Ray ◽  
Particle Contamination ◽  
Emission Microscopy ◽  
Microscopy Techniques ◽  
Scanning Electron

Abstract In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.

Advanced Scan Diagnosis Based Fault Isolation and Defect Identification for Yield Learning

2005 ◽  
Author(s):  
Chris Eddleman ◽  
Nagesh Tamarapalli ◽  
Wu-Tung Cheng
Keyword(s):  
Failure Analysis ◽  
Fault Location ◽  
Effective Means ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Yield Analysis ◽  
Isolation Techniques ◽  
Yield Learning ◽  
Time Required ◽  
Inspection Data

Abstract Yield analysis of sub-micron devices is an ever-increasing challenge. The difficulty is compounded by the lack of in-line inspection data as many companies adopt foundry or fab-less models for acquiring wafers. In this scenario, failure analysis is increasingly critical to help drive yields. Failure analysis is a process of fault isolation, or a method of isolating failures as precisely as possible followed by identification of a physical defect. As the number of transistors and metal layers increase, traditional fault isolation techniques are less successful at isolating a cause of failures. Costs are increasing due to the amount of time needed to locate the physical defect. One solution to the yield analysis problem is scan diagnosis based fault isolation. Previous scan diagnosis based techniques were limited with little information about the type of fault and confidence of diagnosis. With new scan diagnosis algorithms it is now possible to not only isolate, but to identify the type of fault as well as assigning a confidence ranking prior to any destructive analysis. This paper presents multiple case studies illustrating the application of scan diagnosis as an effective means to achieve yield enhancement. The advanced scan diagnostic tool used in this study provides information about the fault type as well as fault location. This information focuses failure analysis efforts toward a suspected defect, decreasing the cycle time required to determine root cause, as well as increasing the over all success rate.

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