Sample Preparation Techniques for Reduced Lateral Heat Distribution and Implications for Non-IR Probing on Integrated Circuits

Author(s):  
Matthew M. Mulholland ◽  
Vladimir V. Vlasyuk ◽  
Robert P. Wadell ◽  
Imran Khan ◽  
Nathan J. Bakken

Abstract Validation techniques on packaged integrated circuit (IC) samples positively impact time to market (TTM) by saving considerable fabrication modification turnaround time and costs. The validation techniques are typically done by working through the backside of the chip. These validation and debug techniques, such as optical probing, use the Solid Immersion Lens (SIL) for imaging and data collection. Solid Immersion Lens based near infrared (NIR) optical probing systems have been an integral function in the product life cycle enabling a fast, reliable, and low defect product to market. For the SIL configuration, the remaining silicon thickness (RST) target is specified to be 50 +/- 5um. The sample preparation tools and techniques to accomplish this have been fully developed and matured enough to provide this specification for all segment form factors. This silicon thickness is also within a sustainable thermal envelope at certain power densities during debug electrical testing and validation. As we move into the next generation of optical probing debug in the visible range, increasing resolution further, new sample preparation methods need to be developed. There are a number of different strategies and techniques to prepare the sample, while also enabling efficient heat transfer. This paper will detail some of the sample preparation techniques as a function of silicon thickness and aspect ratio. These final geometries will then be characterized thermally by investigating lateral heat distribution and junction temperature within the silicon Region of Interest (ROI). Finally, based on this sample preparation and thermal study, implications around debug techniques for optical probing will be discussed.

Author(s):  
Ng Sea Chooi ◽  
Chor Theam Hock ◽  
Ma Choo Thye ◽  
Khoo Poh Tshin ◽  
Dan Bockelman

Abstract Trends in the packaging of semiconductors are towards miniaturization and high functionality. The package-on-package(PoP) with increasing demands is beneficial in cost and space saving. The main failure mechanisms associated with PoP technology, including open joints and warpage, have created a lot of challenges for Assembly and Failure Analysis (FA). This paper outlines the sample preparation process steps to overcome the challenges to enable successful failure analysis and optical probing.


Author(s):  
M.S. Wei ◽  
H.B. Chong ◽  
S.H. Lim ◽  
C. Richardson

Abstract High resolution laser imaging, using high numerical aperture (NA) solid immersion lens (SIL) for backside fault isolation imposes stringent sample preparation requirements; as a result of the short focal length of SIL, a die must be thinned to a targeted thickness with less than a ±5 μm silicon thickness variation across the entire die. Flip chip packaged dice suffer from warpage due to various package sizes and substrate thicknesses. Such broad spectrums of part geometries pose a great challenge to meet such silicon planarity requirements. As relaxation of the packaged silicon during polishing causes the warpage profile to change dynamically and unpredictably throughout the thinning process, it has become an added challenge to meet the stringent sample preparation requirements. To overcome the stochastic nature of this problem, a two-step polishing recipe consisting of computer numerical control (CNC) mechanical milling and polishing processes has been developed to achieve sufficient silicon thickness uniformity to enable SIL imaging across an entire silicon chip as large as approximately 20 mm x 15 mm.


Author(s):  
Earl R. Walter ◽  
Glen H. Bryant

With the development of soft, film forming latexes for use in paints and other coatings applications, it became desirable to develop new methods of sample preparation for latex particle size distribution studies with the electron microscope. Conventional latex sample preparation techniques were inadequate due to the pronounced tendency of these new soft latex particles to distort, flatten and fuse on the substrate when they dried. In order to avoid these complications and obtain electron micrographs of undistorted latex particles of soft resins, a freeze-dry, cold shadowing technique was developed. The method has now been used in our laboratory on a routine basis for several years.The cold shadowing is done in a specially constructed vacuum system, having a conventional mechanical fore pump and oil diffusion pump supplying vacuum. The system incorporates bellows type high vacuum valves to permit a prepump cycle and opening of the shadowing chamber without shutting down the oil diffusion pump. A baffeled sorption trap isolates the shadowing chamber from the pumps.


Author(s):  
P. B. Basham ◽  
H. L. Tsai

The use of transmission electron microscopy (TEM) to support process development of advanced microelectronic devices is often challenged by a large amount of samples submitted from wafer fabrication areas and specific-spot analysis. Improving the TEM sample preparation techniques for a fast turnaround time is critical in order to provide a timely support for customers and improve the utilization of TEM. For the specific-area sample preparation, a technique which can be easily prepared with the least amount of effort is preferred. For these reasons, we have developed several techniques which have greatly facilitated the TEM sample preparation.For specific-area analysis, the use of a copper grid with a small hole is found to be very useful. With this small-hole grid technique, TEM sample preparation can be proceeded by well-established conventional methods. The sample is first polished to the area of interest, which is then carefully positioned inside the hole. This polished side is placed against the grid by epoxy Fig. 1 is an optical image of a TEM cross-section after dimpling to light transmission.


Author(s):  
Jim Colvin ◽  
Timothy Hazeldine ◽  
Heenal Patel

Abstract The standard requirement for FA Engineers needing to remove components from a board, prior to decapsulation or sample preparation, is shown to be greatly reduced, by the methods discussed here. By using a mechanical selected area preparation system with an open-design it is possible to reach all required areas of a large printed circuit board (PCB) or module to prepare a single component ‘in situ’. This makes subsequent optical or electrical testing faster and often more convenient to accomplish. Electronic End-pointing and 3D curvature compensation methods can often be used in parallel with sample prep techniques to further improve the consistency and efficacy of the decapsulation and thinning uniformity and final remaining silicon thickness (RST). Board level prep eliminates the worry of rework removal of BGA packages and the subsequent risk of damage to the device. Since the entire board is mounted, the contamination is restricted to the die surface and can be kept from the underside ball connections unlike current liquid immersion methods of package thinning or delayering. Since the camera is in line with the abrasion interface, imaging is real time during the entire milling and thinning process. Recent advances in automated tilt-table design have meant that a specific component’s angular orientation can be optimized for sample preparation. Improved tilt table technology also allows for improved mounting capability for boards of many types and sizes. The paper describes methods for decapsulation, thinning and backside polishing of a part ‘in situ’ on the polishing machine and allows the system to operate as a probe station for monitoring electrical characteristics while thinning. Considerations for designing board-level workholders are described – for boards that that are populated with components on one or even both sides. Using the techniques described, the quality of sample preparation and control is on a par with the processing of single package-level devices.


Author(s):  
Jason H. Lagar ◽  
Rudolf A. Sia

Abstract Most Wafer Level Chip Scale Package (WLCSP) units returned by customers for failure analysis are mounted on PCB modules with an epoxy underfill coating. The biggest challenge in failure analysis is the sample preparation to remove the WLCSP device from the PCB without inducing any mechanical defect. This includes the removal of the underfill material to enable further electrical verification and fault isolation analysis. This paper discusses the evaluations conducted in establishing the WLCSP demounting process and removal of the epoxy underfill coating. Combinations of different sample preparation techniques and physical failure analysis steps were evaluated. The established process enabled the electrical verification, fault isolation and further destructive analysis of WLCSP customer returns mounted on PCB and with an epoxy underfill coating material. This paper will also showcase some actual full failure analysis of WLCSP customer returns where the established process played a vital role in finding the failure mechanism.


Author(s):  
Hyoung H. Kang ◽  
Michael A. Gribelyuk ◽  
Oliver D. Patterson ◽  
Steven B. Herschbein ◽  
Corey Senowitz

Abstract Cross-sectional style transmission electron microscopy (TEM) sample preparation techniques by DualBeam (SEM/FIB) systems are widely used in both laboratory and manufacturing lines with either in-situ or ex-situ lift out methods. By contrast, however, the plan view TEM sample has only been prepared in the laboratory environment, and only after breaking the wafer. This paper introduces a novel methodology for in-line, plan view TEM sample preparation at the 300mm wafer level that does not require breaking the wafer. It also presents the benefit of the technique on electrically short defects. The methodology of thin lamella TEM sample preparation for plan view work in two different tool configurations is also presented. The detailed procedure of thin lamella sample preparation is also described. In-line, full wafer plan view (S)TEM provides a quick turn around solution for defect analysis in the manufacturing line.


2020 ◽  
Vol 16 ◽  
Author(s):  
Mustafa Çelebier ◽  
Merve Nenni

Background: Metabolomics has gained importance in clinical applications over the last decade. Metabolomics studies are significant because the systemic metabolome is directly affected by disease conditions. Metabolome-based biomarkers are actively being developed for early diagnosis and to indicate the stage of specific diseases. Additionally, understanding the effect of an intervention on a living organism at the molecular level is a crucial strategy for understanding novel or unexpected biological processes. Results: The simultaneous improvements in advanced analytical techniques, sample preparation techniques, computer technology, and databank contents has enabled more valuable scientific information to be gained from metabolomics than ever before. With over 15,000 known endogenous metabolites, there is no single analytical technique capable of analyzing the whole metabolome. However, capillary electrophoresis-mass spectrometry (CE-MS) is a unique technique used to analyze an important portion of metabolites not accessible by liquid chromatography or gas chromatography techniques. The analytical capability of CE, combined with recent sample preparation techniques focused on extracting polar-ionic compounds, make CE-MS a perfect technique for metabolomic studies. Conclusion: Here, previous reviews of CE-MS based metabolomics are evaluated to highlight recent improvements in this technique. Specifically, we review papers from the last two years (2018 and 2019) on CE-MS based metabolomics. The current situation and the challenges facing metabolomic studies are discussed to reveal the high potential of CE-MS for further studies, especially in biomarker development studies.


Author(s):  
M V Burachevskaya ◽  
T M Minkina ◽  
S S Mandzhieva ◽  
V S Cicuashvili ◽  
E S Fedorenko ◽  
...  

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