scholarly journals Chip Recombination Method in Planar Deprocessing – A Solution for Failure Analysis on Chip Edge Defects

Author(s):  
Kah Chin Cheong ◽  
Gabriel Pragay ◽  
Wiwy Wudjud ◽  
Rafael Lainez

Abstract Planar deprocessing is a vital failure analysis (FA) technique for semiconductor chip reverse engineering. The basic concept of planar deprocessing is to remove all the “unnecessary” materials of a chip to expose an area of interest (AOI) and maintain the chip planarity and surface evenness. Finger deprocessing is one of the common techniques applied to this concept. This technique is essential in physical FA, especially for advanced bulk fin field-effect transistor (FinFET) devices. The success of finger deprocessing technique depends on certain factors, one of which is the location of AOI region. Application of finger deprocessing becomes incredibly challenging for AOI close to chip edge due to the chip edge effect, i. e. the chip edge is deprocessed much faster than the chip center. Plasma focused ion beam (PFIB) planar deprocessing is the primary solution to solve this problem. However, the PFIB capability is a luxury tool for most analysis labs. To overcome this challenge, a novel chip recombination method is introduced. With this method, planar deprocess can be achieved by conventional finger deprocessing technique and more importantly can be applied in general analysis labs. This paper will discuss the newly developed method in a step-by-step guide basis and show two cases with AOI(s) in the chip edge region to demonstrate its capability.

2018 ◽  
Author(s):  
C.S. Bonifacio ◽  
P. Nowakowski ◽  
M.J. Campin ◽  
M.L. Ray ◽  
P.E. Fischione

Abstract Transmission electron microscopy (TEM) specimens are typically prepared using the focused ion beam (FIB) due to its site specificity, and fast and accurate thinning capabilities. However, TEM and high-resolution TEM (HRTEM) analysis may be limited due to the resulting FIB-induced artifacts. This work identifies FIB artifacts and presents the use of argon ion milling for the removal of FIB-induced damage for reproducible TEM specimen preparation of current and future fin field effect transistor (FinFET) technologies. Subsequently, high-quality and electron-transparent TEM specimens of less than 20 nm are obtained.


1999 ◽  
Vol 595 ◽  
Author(s):  
M. Kuball ◽  
M. Benyoucef ◽  
F.H. Morrissey ◽  
C.T. Foxon

AbstractWe report on the nano-fabrication of GaN/AlGaN device structures using focused ion beam (FIB) etching, illustrated on a GaN/AlGaN heterostructure field effect transistor (HFET). Pillars as small as 20nm to 300nm in diameter were fabricated from the GaN/AlGaN HFET. Micro-photoluminescence and UV micro-Raman maps were recorded from the FIB-etched pattern to assess its material quality. Photoluminescence was detected from 300nm-size GaN/AlGaN HFET pillars, i.e., from the AlGaN as well as the GaN layers in the device structure, despite the induced etch damage. Properties of the GaN and the AlGaN layers in the FIB-etched areas were mapped using UV Micro-Raman spectroscopy. Damage introduced by FIB-etching was assessed. The fabricated nanometer-size GaN/AlGaN structures were found to be of good quality. The results demonstrate the potential of FIB-etching for the nano-fabrication of III-V nitride devices.


2018 ◽  
Author(s):  
Sze Yee Tan ◽  
Chiu Soon Wong ◽  
Chea Wee Lo ◽  
Cin Sheng Goh

Abstract In the back-end assembly process, all of the packages will be tested prior to disposition to the customers in order to filter out any device with failure. For a reject unit with an unknown failure mechanism, it will be subjected to a comprehensive failure analysis (FA) to identify the root cause of the failure. Non-destructive verification, following by front-side decapsulation and internal physical inspection is the common way to visualise and identify the physical defect that usually causes the failure of a device during the back-end assembly process. For certain failures, visualization of the defect might not be straight forward after the decapsulation because the defect may be embedded or buried underneath a layer or wedge bond on the die. In this case, a more complicated FA analysis flow which comprises various precision techniques such as parallel lapping, hotspot localisation and focused-ion-beam (FIB) analyses will be needed to thin down the top layer/wedge bond for a precise localisation of the defect prior to precision analysis by FIB. However, the process to thin down the top layer/wedge bond with an exposed die of a partially decapsulated package is a tricky job as artefacts such as crack/scratches on die are likely to be introduced during the process of polishing. Also it is relatively difficult to control the thickness and levelling of the top layer/wedge bond during the thinning process. In this work, we developed a method that allows the analyst to re-cap the partially decapped package, and also to precisely measure and thin down the top layer to an accuracy of less than < 2um without the introduction of artefacts.


Author(s):  
J. David Casey ◽  
Thomas J. Gannon ◽  
Alex Krechmer ◽  
David Monforte ◽  
Nicholas Antoniou ◽  
...  

Abstract Advances in FIB (focused ion beam) chemical processes and in the Ga (gallium) beam profile are discussed; these advances are necessary for the successful failure analysis, circuit edit and design verification of advanced, sub-0.13µm Cu devices. Included in this article are: a novel FIB method (CopperRx) for smoothly milling thick, large grained Cu lines; H2O and O2 processes for cleanly cutting thin, smaller grained Cu lines, thereby forming electrically open interconnects; a XeF2 GAE (gas assisted etching) process for etching low k, CVD dielectrics such as F and C doped SiO2; H2O and XeF2 GAE processes for etching low k, spin-on, organic dielectrics such as SiLK; a recently developed recipe for the deposition of SiO2 based material with intermediate resistivity (106 µohm·cm) which is useful in the design verification of frequency sensitive, high speed analog and SOC (system on chip) circuits; an improved, more Gaussian Ga beam with less current density in the beam tails (VisION column) which provides higher resolution, real time images needed for end-point detection on sub 0.13µm features during milling.


2000 ◽  
Vol 5 (S1) ◽  
pp. 950-956
Author(s):  
M. Kuball ◽  
M. Benyoucef ◽  
F.H. Morrissey ◽  
C.T. Foxon

We report on the nano-fabrication of GaN/AlGaN device structures using focused ion beam (FIB) etching, illustrated on a GaN/AlGaN heterostructure field effect transistor (HFET). Pillars as small as 20nm to 300nm in diameter were fabricated from the GaN/AlGaN HFET. Micro-photoluminescence and UV micro-Raman maps were recorded from the FIB-etched pattern to assess its material quality. Photoluminescence was detected from 300nm-size GaN/AlGaN HFET pillars, i.e., from the AlGaN as well as the GaN layers in the device structure, despite the induced etch damage. Properties of the GaN and the AlGaN layers in the FIB-etched areas were mapped using UV Micro-Raman spectroscopy. Damage introduced by FIB-etching was assessed. The fabricated nanometer-size GaN/AlGaN structures were found to be of good quality. The results demonstrate the potential of FIB-etching for the nano-fabrication of III-V nitride devices.


2008 ◽  
Vol 8 (1) ◽  
pp. 457-460 ◽  
Author(s):  
Cheng Qi ◽  
Yaswanth Rangineni ◽  
Gary Goncher ◽  
Raj Solanki ◽  
Kurt Langworthy ◽  
...  

Si0.5Ge0.5 nanowires have been utilized to fabricate source-drain channels of p-type field effect transistors (p-FETs). These transistors were fabricated using two methods, focused ion beam (FIB) and electron beam lithography (EBL). The electrical analyses of these devices show field effect transistor characteristics. The boron-doped SiGe p-FETs with a high-k (HfO2) insulator and Pt electrodes, made via FIB produced devices with effective hole mobilities of about 50 cm2V−1s−1. Similar transistors with Ti/Au electrodes made via EBL had effective hole mobilities of about 350 cm2V−1s−1.


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