A Method to Enhance the Front-Side Lapping Process for Localisation of Sub-Surface Defect for Advanced Packages

2018 ◽  
Author(s):  
Sze Yee Tan ◽  
Chiu Soon Wong ◽  
Chea Wee Lo ◽  
Cin Sheng Goh
Keyword(s):  
Failure Analysis ◽  
Surface Defect ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Assembly Process ◽  
Front Side ◽  
Root Cause ◽  
The Common ◽  
Thinning Process ◽  
Non Destructive

Abstract In the back-end assembly process, all of the packages will be tested prior to disposition to the customers in order to filter out any device with failure. For a reject unit with an unknown failure mechanism, it will be subjected to a comprehensive failure analysis (FA) to identify the root cause of the failure. Non-destructive verification, following by front-side decapsulation and internal physical inspection is the common way to visualise and identify the physical defect that usually causes the failure of a device during the back-end assembly process. For certain failures, visualization of the defect might not be straight forward after the decapsulation because the defect may be embedded or buried underneath a layer or wedge bond on the die. In this case, a more complicated FA analysis flow which comprises various precision techniques such as parallel lapping, hotspot localisation and focused-ion-beam (FIB) analyses will be needed to thin down the top layer/wedge bond for a precise localisation of the defect prior to precision analysis by FIB. However, the process to thin down the top layer/wedge bond with an exposed die of a partially decapsulated package is a tricky job as artefacts such as crack/scratches on die are likely to be introduced during the process of polishing. Also it is relatively difficult to control the thickness and levelling of the top layer/wedge bond during the thinning process. In this work, we developed a method that allows the analyst to re-cap the partially decapped package, and also to precisely measure and thin down the top layer to an accuracy of less than < 2um without the introduction of artefacts.

Failure Analysis Work Flow for Electrical Shorts in Triple Stacked 3D TSV Daisy Chains

2015 ◽  
Vol 2015 (1) ◽  
pp. 000469-000473 ◽  
Author(s):  
J. Gaudestad ◽  
A. Orozco ◽  
I. De Wolf ◽  
T. Wang ◽  
T. Webers ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Fault Isolation ◽  
Root Cause ◽  
Current Path ◽  
Dual Beam ◽  
Resolution Imaging ◽  
Magnetic Field Imaging ◽  
Non Destructive

In this paper we show an efficient workflow that combines Magnetic Field Imaging (MFI) and Dual Beam Plasma Focused Ion Beam (DB-PFIB) for fast and efficient Fault Isolation and root cause analysis in 2.5/3D devices. The work proves MFI is the best method for Electric Fault Isolation (EFI) of short failures in 2.5/3D Through Silicon Via (TSV) triple stacked devices in a true non-destructive way by imaging the current path. To confirm the failing locations and to do Physical Failure Analysis (PFA), a DB-PFIB system was used for cross sectioning and volume analysis of the TSV structures and high resolution imaging of the identified defects. With a DB-PFIB, the fault is exposed and analyzed without any sample prep artifacts seen in mechanical polishing or laser preparation techniques and done in a considerably shorter amount of time than that required when using a traditional Gallium Focused Ion Beam (FIB).

Failure Analysis Work Flow for Electrical Shorts in Triple Stacked 3D TSV Daisy Chains

2014 ◽  
Author(s):  
J. Gaudestad ◽  
A. Orozco ◽  
I. De Wolf ◽  
T. Wang ◽  
T. Webers ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Fault Isolation ◽  
Root Cause ◽  
Current Path ◽  
Dual Beam ◽  
Resolution Imaging ◽  
Magnetic Field Imaging ◽  
Non Destructive

Abstract In this paper we show an efficient workflow that combines Magnetic Field Imaging (MFI) and Dual Beam Plasma Focused Ion Beam (DB-PFIB) for fast and efficient Fault Isolation and root cause analysis in 2.5/3D devices. The work proves MFI is the best method for Electric Fault Isolation (EFI) of short failures in 2.5/3D Through Silicon Via (TSV) triple stacked devices in a true non-destructive way by imaging the current path. To confirm the failing locations and to do Physical Failure Analysis (PFA), a DB-PFIB system was used for cross sectioning and volume analysis of the TSV structures and high resolution imaging of the identified defects. With a DB-PFIB, the fault is exposed and analyzed without any sample prep artifacts seen in mechanical polishing or laser preparation techniques and done in a considerably shorter amount of time than that required when using a traditional Gallium Focused Ion Beam (FIB).

Localization Techniques on a 0.15um CMOS Device: Charge Pump Failure Analysis

2002 ◽  
Author(s):  
Hui Pan ◽  
Thomas Gibson
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Charge Pump ◽  
Front Side ◽  
Pump Failure ◽  
Electrical Failure ◽  
Optical Proximity Correction ◽  
A Charge

Abstract In recent years, there have been many advances in the equipment and techniques used to isolate faults. There are many options available to the failure analyst. The available techniques fall into the categories of electrical, photonic, thermal and electron/ion beam [1]. Each technique has its advantages and its limitations. In this paper, we introduce a case of successful failure analysis using a combination of several fault localization techniques on a 0.15um CMOS device with seven layers of metal. It includes electrical failure mode characterization, front side photoemission, backside photoemission, Focused Ion Beam (FIB), Scanning Electron Microscope (SEM) and liquid crystal. Electrical characterization along with backside photoemission proved most useful in this case as a poly short problem was found to be causing a charge pump failure. A specific type of layout, often referred to as a hammerhead layout, and the use of Optical Proximity Correction (OPC) contributed to the poly level shorts.

Failure Analysis Strategies for Multistacked Memory Devices with TSV Interconnects

2015 ◽  
Author(s):  
Frank Altmann ◽  
Christian Grosse ◽  
Falk Naumann ◽  
Jens Beyersdorfer ◽  
Tony Veches
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Memory Devices ◽  
Metallographic Cross Section ◽  
Electron Beam Induced Current ◽  
Thermal Simulations ◽  
Lock In ◽  
Non Destructive

Abstract In this paper we will demonstrate new approaches for failure analysis of memory devices with multiple stacked dies and TSV interconnects. Therefore, TSV specific failure modes are studied on daisy chain test samples. Two analysis flows for defect localization implementing Electron Beam Induced Current (EBAC) imaging and Lock-in-Thermography (LIT) as well as adapted Focused Ion Beam (FIB) preparation and defect characterization by electron microscopy will be discussed. The most challenging failure mode is an electrical short at the TSV sidewall isolation with sub-micrometer dimensions. It is shown that the leakage path to a certain TSV within the stack can firstly be located by applying LIT to a metallographic cross section and secondly pinpointing by FIB/SEM cross-sectioning. In order to evaluate the potential of non-destructive determination of the lateral defect position, as well as the defect depth from only one LIT measurement, 2D thermal simulations of TSV stacks with artificial leakages are performed calculating the phase shift values per die level.

scholarly journals Localizing Heat-Generating Defects Using Fluorescent Microthermal Imaging

1996 ◽  
Author(s):  
P. Tangyunyong ◽  
A.Y. Liang ◽  
A.W. Righter ◽  
D.L. Barton ◽  
J.M. Soden
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Uv Light ◽  
Ion Beam ◽  
Sample Surface ◽  
Analysis Tool ◽  
Temperature Dependent ◽  
Root Cause ◽  
Ideal Situation ◽  
Sem Imaging

Abstract Fluorescent microthermal imaging (FMI) involves coating a sample surface with a thin fluorescent film that, upon exposure to UV light source, emits temperature-dependent fluorescence [1-7]. The principle behind FMI was thoroughly reviewed at the ISTFA in 1994 [8, 9]. In two recent publications [10,11], we identified several factors in film preparation and data processing that dramatically improved the thermal resolution and sensitivity of FMI. These factors include signal averaging, the use of base mixture films, film stabilization and film curing. These findings significantly enhance the capability of FMI as a failure analysis tool. In this paper, we show several examples that use FMI to quickly localize heat-generating defects ("hot spots"). When used with other failure analysis techniques such as focused ion beam (FIB) cross sectioning and scanning electron microscope (SEM) imaging, we demonstrate that FMI is a powerful tool to efficiently identify the root cause of failures in complex ICs. In addition to defect localization, we use a failing IC to determine the sensitivity of FMI (i.e., the lowest power that can be detected) in an ideal situation where the defects are very localized and near the surface.

Magnetic Head Shorting Failure Analysis

2017 ◽  
Author(s):  
Liang Hong ◽  
Jia Li ◽  
Haifeng Wang
Keyword(s):  
Electron Microscopy ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Tem Analysis ◽  
Resistance Change ◽  
Root Cause ◽  
Transmission Electron ◽  
Root Cause Failure Analysis ◽  
Metal Layers

Abstract This paper provides an innovative root cause failure analysis method that combines multiple failure analysis (FA) techniques to narrow down and expose the shorting location and allow the material analysis of the shorting defect. It begins with a basic electrical testing to narrow down shorting metal layers, then utilizing mechanical lapping to expose over coat layers. This is followed by optical beam induced resistance change imaging to further narrow down the shorting location. Scanning electron microscopy and optical imaging are used together with focused ion beam milling to slice and view through the potential shorting area until the shorting defect is exposed. Finally, transmission electron microscopy (TEM) sample is prepared, and TEM analysis is carried out to pin point the root cause of the shorting. This method has been demonstrated successfully on Western Digital inter-metal layers shorting FA.

Application of Focused Ion Beam System as A Defect Localization and Root Cause Analysis Tool

2001 ◽  
Author(s):  
C.C. Ooi ◽  
K.H. Siek ◽  
K.S. Sim
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Fault Isolation ◽  
Analysis Tool ◽  
Root Cause ◽  
Beam System ◽  
Defect Localization ◽  
Challenging Environment ◽  
Microprocessor Technology

Abstract Focused ion beam system has been widely used as a critical failure analysis tool as microprocessor technology advances at a ramping speed. It has become an essential step in failure analysis to reveal physical defects post electrical fault isolation. In this highly competitive and challenging environment prevalent today, failure analysis throughput time is of utmost important. Therefore quick, efficient and reliable physical failure analysis technique is needed to avoid potential issues from becoming bigger. This paper will discuss the applications of FIB as a defect localization and root cause determination tool through the passive charge contrast technique and pattern FIB analysis.

Pulse Laser Ablation Techniques for IC Package Substrate Modifications and Validation

2016 ◽  
Author(s):  
Matthew M. Mulholland ◽  
Ahmed A. Helmy ◽  
Anthony V. Dao
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Pulse Laser ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Back Side ◽  
Front Side ◽  
Local Approach ◽  
Ic Package ◽  
Level Analysis

Abstract Post silicon validation techniques specifically Focused Ion Beam (FIB) circuit editing and Failure Analysis (FA) require sample preparation on Integrated Circuits (IC). Although these preparation techniques are typically done globally across the encapsulated and silicon packaging materials, in some scenarios with tight mechanical or thermal boundary conditions, only a local approach can be attempted for the analysis. This local approach to access the underlying features, such as circuits, solder bumps, and electrical traces can be divided into two modification approaches. The back side approach is typically done for die level analysis by de-processing through encapsulated mold compound and silicon gaining access to the silicon transistor level. On the other hand, the front side approach is typically used for package level analysis by de-processing the ball grid array (BGA) and package substrate layers. Both of these local de-processing approaches can be done by using the conventional Laser Chemical Etching (LCE) platforms. The focus of this paper will be to investigate a front side modification approach to provide substrate material removal solutions. Process details and techniques will be discussed to gain access to metal signals for further failure analysis and debug. A pulse laser will be used at various processing stages to de-process IC package substrate materials.

scholarly journals Chip Recombination Method in Planar Deprocessing – A Solution for Failure Analysis on Chip Edge Defects

2021 ◽  
Author(s):  
Kah Chin Cheong ◽  
Gabriel Pragay ◽  
Wiwy Wudjud ◽  
Rafael Lainez
Keyword(s):  
Failure Analysis ◽  
Field Effect Transistor ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Semiconductor Chip ◽  
Area Of Interest ◽  
Edge Defects ◽  
The Common ◽  
Effect Transistor ◽  
On Chip

Abstract Planar deprocessing is a vital failure analysis (FA) technique for semiconductor chip reverse engineering. The basic concept of planar deprocessing is to remove all the “unnecessary” materials of a chip to expose an area of interest (AOI) and maintain the chip planarity and surface evenness. Finger deprocessing is one of the common techniques applied to this concept. This technique is essential in physical FA, especially for advanced bulk fin field-effect transistor (FinFET) devices. The success of finger deprocessing technique depends on certain factors, one of which is the location of AOI region. Application of finger deprocessing becomes incredibly challenging for AOI close to chip edge due to the chip edge effect, i. e. the chip edge is deprocessed much faster than the chip center. Plasma focused ion beam (PFIB) planar deprocessing is the primary solution to solve this problem. However, the PFIB capability is a luxury tool for most analysis labs. To overcome this challenge, a novel chip recombination method is introduced. With this method, planar deprocess can be achieved by conventional finger deprocessing technique and more importantly can be applied in general analysis labs. This paper will discuss the newly developed method in a step-by-step guide basis and show two cases with AOI(s) in the chip edge region to demonstrate its capability.

Defect Localization and Root Cause Analysis on e-Fuse Read Reliability Failure

2014 ◽  
Author(s):  
Hung Chin Chen ◽  
Chih Yang Tsai ◽  
Shih Yuan Liu ◽  
Yu Pang Chang ◽  
Jian Chang Lin
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Metal Layer ◽  
Ion Beam ◽  
Fault Isolation ◽  
Resistance Change ◽  
Cause Analysis ◽  
Root Cause ◽  
Failure Location ◽  
Rate Of Failure

Abstract Fault isolation is the most important step for Failure Analysis (FA), and it is closely linked with the success rate of failure mechanism finding. In this paper, we will introduce a case that hard to debug with traditional FA skills. In order to find out its root cause, several advanced techniques such as layout tracing, circuit edit and Infrared Ray–Optical Beam Induced Resistance Change (IR-OBIRCH) analysis had been applied. The circuit edit was performed following layout tracing for depositing probing pads by Focused Ion Beam (FIB). Then, IR-OBIRCH analysis with biasing on the two FIB deposited probing pads and a failure location was detected. Finally, the root cause of inter- metal layer bridge was found in subsequent physical failure analysis.

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