scholarly journals Implications of NVM Based Storage on Memory Subsystem Management

2020 ◽  
Vol 10 (3) ◽  
pp. 999
Author(s):  
Hyokyung Bahn ◽  
Kyungwoon Cho
Keyword(s):  
Random Access ◽  
Disk Drive ◽  
Main Memory ◽  
Memory Storage ◽  
Storage Device ◽  
Storage Devices ◽  
Large Memory ◽  
Memory Subsystems ◽  
Non Volatile Memory ◽  
Management Techniques

Recently, non-volatile memory (NVM) has advanced as a fast storage medium, and legacy memory subsystems optimized for DRAM (dynamic random access memory) and HDD (hard disk drive) hierarchies need to be revisited. In this article, we explore the memory subsystems that use NVM as an underlying storage device and discuss the challenges and implications of such systems. As storage performance becomes close to DRAM performance, existing memory configurations and I/O (input/output) mechanisms should be reassessed. This article explores the performance of systems with NVM based storage emulated by the RAMDisk under various configurations. Through our measurement study, we make the following findings. (1) We can decrease the main memory size without performance penalties when NVM storage is adopted instead of HDD. (2) For buffer caching to be effective, judicious management techniques like admission control are necessary. (3) Prefetching is not effective in NVM storage. (4) The effect of synchronous I/O and direct I/O in NVM storage is less significant than that in HDD storage. (5) Performance degradation due to the contention of multi-threads is less severe in NVM based storage than in HDD. Based on these observations, we discuss a new PC configuration consisting of small memory and fast storage in comparison with a traditional PC consisting of large memory and slow storage. We show that this new memory-storage configuration can be an alternative solution for ever-growing memory demands and the limited density of DRAM memory. We anticipate that our results will provide directions in system software development in the presence of ever-faster storage devices.

scholarly journals InK: In-Kernel Key-Value Storage with Persistent Memory

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1913
Author(s):  
Minjong Ha ◽  
Sang-Hoon Kim
Keyword(s):  
High Performance ◽  
File Systems ◽  
Cloud Service ◽  
Main Memory ◽  
Storage Device ◽  
Storage Devices ◽  
Persistent Memory ◽  
Non Volatile Memory ◽  
Long Time ◽  
Block Based

Block-based storage devices exhibit different characteristics from main memory, and applications and systems have been optimized for a long time considering the characteristics in mind. However, emerging non-volatile memory technologies are about to change the situation. Persistent Memory (PM) provides a huge, persistent, and byte-addressable address space to the system, thereby enabling new opportunities for systems software. However, existing applications are usually apt to indirectly utilize PM as a storage device on top of file systems. This makes applications and file systems perform unnecessary operations and amplify I/O traffic, thereby under-utilizing the high performance of PM. In this paper, we make the case for an in-Kernel key-value storage service optimized for PM, called InK. While providing the persistence of data at a high performance, InK considers the characteristics of PM to guarantee the crash consistency. To this end, InK indexes key-value pairs with B+ tree, which is more efficient on PM. We implemented InK based on the Linux kernel and evaluated its performance with Yahoo Cloud Service Benchmark (YCSB) and RocksDB. Evaluation results confirms that InK has advantages over LSM-tree-based key-value store systems in terms of throughput and tail latency.

scholarly journals Q-Selector-Based Prefetching Method for DRAM/NVM Hybrid Main Memory System

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2158
Author(s):  
Jeong-Geun Kim ◽  
Shin-Dug Kim ◽  
Su-Kyung Yoon
Keyword(s):  
Performance Status ◽  
Random Access ◽  
Memory Systems ◽  
Memory System ◽  
Main Memory ◽  
Learning Method ◽  
Q Learning ◽  
Data Intensive ◽  
Big Data Applications ◽  
Non Volatile Memory

This research is to design a Q-selector-based prefetching method for a dynamic random-access memory (DRAM)/ Phase-change memory (PCM)hybrid main memory system for memory-intensive big data applications generating irregular memory accessing streams. Specifically, the proposed method fully exploits the advantages of two-level hybrid memory systems, constructed as DRAM devices and non-volatile memory (NVM) devices. The Q-selector-based prefetching method is based on the Q-learning method, one of the reinforcement learning algorithms, which determines a near-optimal prefetcher for an application’s current running phase. For this, our model analyzes real-time performance status to set the criteria for the Q-learning method. We evaluate the Q-selector-based prefetching method with workloads from data mining and data-intensive benchmark applications, PARSEC-3.0 and graphBIG. Our evaluation results show that the system achieves approximately 31% performance improvement and increases the hit ratio of the DRAM-cache layer by 46% on average compared to a PCM-only main memory system. In addition, it achieves better performance results compared to the state-of-the-art prefetcher, access map pattern matching (AMPM) prefetcher, by 14.3% reduction of execution time and 12.89% of better CPI enhancement.

scholarly journals Self-rectifying resistive memory in passive crossbar arrays

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Kanghyeok Jeon ◽  
Jeeson Kim ◽  
Jin Joo Ryu ◽  
Seung-Jong Yoo ◽  
Choongseok Song ◽  
...  
Keyword(s):  
Deep Learning ◽  
Large Scale ◽  
Supply Voltage ◽  
Random Access ◽  
Memory Cell ◽  
Complementary Metal Oxide Semiconductor ◽  
Main Memory ◽  
Oxide Semiconductor ◽  
Resistive Memory ◽  
Non Volatile Memory

AbstractConventional computing architectures are poor suited to the unique workload demands of deep learning, which has led to a surge in interest in memory-centric computing. Herein, a trilayer (Hf0.8Si0.2O2/Al2O3/Hf0.5Si0.5O2)-based self-rectifying resistive memory cell (SRMC) that exhibits (i) large selectivity (ca. 104), (ii) two-bit operation, (iii) low read power (4 and 0.8 nW for low and high resistance states, respectively), (iv) read latency (<10 μs), (v) excellent non-volatility (data retention >104 s at 85 °C), and (vi) complementary metal-oxide-semiconductor compatibility (maximum supply voltage ≤5 V) is introduced, which outperforms previously reported SRMCs. These characteristics render the SRMC highly suitable for the main memory for memory-centric computing which can improve deep learning acceleration. Furthermore, the low programming power (ca. 18 nW), latency (100 μs), and endurance (>106) highlight the energy-efficiency and highly reliable random-access memory of our SRMC. The feasible operation of individual SRMCs in passive crossbar arrays of different sizes (30 × 30, 160 × 160, and 320 × 320) is attributed to the large asymmetry and nonlinearity in the current-voltage behavior of the proposed SRMC, verifying its potential for application in large-scale and high-density non-volatile memory for memory-centric computing.

scholarly journals Mapping Datasets to Object Storage System

2020 ◽  
Vol 245 ◽  
pp. 04037
Author(s):  
Xiaowei Aaron Chu ◽  
Jeff LeFevre ◽  
Aldrin Montana ◽  
Dana Robinson ◽  
Quincey Koziol ◽  
...  
Keyword(s):  
Storage Systems ◽  
Distributed Storage ◽  
Storage System ◽  
Random Access ◽  
Data Partitioning ◽  
Data Layout ◽  
Storage Devices ◽  
Storage Servers ◽  
Non Volatile Memory ◽  
Volatile Memory

Access libraries such as ROOT[1] and HDF5[2] allow users to interact with datasets using high level abstractions, like coordinate systems and associated slicing operations. Unfortunately, the implementations of access libraries are based on outdated assumptions about storage systems interfaces and are generally unable to fully benefit from modern fast storage devices. For example, access libraries often implement buffering and data layout that assume that large, single-threaded sequential access patterns are causing less overall latency than small parallel random access: while this is true for spinning media, it is not true for flash media. The situation is getting worse with rapidly evolving storage devices such as non-volatile memory and ever larger datasets. This project explores distributed dataset mapping infrastructures that can integrate and scale out existing access libraries using Ceph’s extensible object model, avoiding re-implementation or even modifications of these access libraries as much as possible. These programmable storage extensions coupled with our distributed dataset mapping techniques enable: 1) access library operations to be offloaded to storage system servers, 2) the independent evolution of access libraries and storage systems and 3) fully leveraging of the existing load balancing, elasticity, and failure management of distributed storage systems like Ceph. They also create more opportunities to conduct storage server-local optimizations specific to storage servers. For example, storage servers might include local key/value stores combined with chunk stores that require different optimizations than a local file system. As storage servers evolve to support new storage devices like non-volatile memory, these server-local optimizations can be implemented while minimizing disruptions to applications. We will report progress on the means by which distributed dataset mapping can be abstracted over particular access libraries, including access libraries for ROOT data, and how we address some of the challenges revolving around data partitioning and composability of access operations.

scholarly journals Generation of address sequences with a given switching activity

Informatics ◽  
2020 ◽  
Vol 17 (1) ◽  
pp. 47-62
Author(s):  
V. N. Yarmolik ◽  
N. A. Shevchenko
Keyword(s):  
Random Access ◽  
Test Sequence ◽  
Storage Device ◽  
Practical Implementation ◽  
Universal Method ◽  
Switching Activity ◽  
Storage Devices ◽  
Mathematical Expressions ◽  
Generating Matrix ◽  
March Tests

The relevance of testing modern computing systems and, first of all, their storage devices is shown. The studies are based on the use of a universal method for generating the address sequences with desired      properties for multiple March tests of random access memory devices.  The modification of economical method of Antonov and Saleev is used as mathematical model to form Sobol sequences. For this model a structural diagram of its hardware implementation is presented, where the storage device for storing direction numbers is used as the basis. The set of multitudes makes up the generating matrix. It is noted that the form of the generating matrix determines the basic properties of the generated sequences. Mathematical expressions are obtained that make it possible to estimate the limiting values of switching activity, both of the sequence itself and of its individual bits. A technique is proposed for the synthesis of generators of address sequences with a given switching activity both of its individual bits and of the sequence as a whole. Examples of the application of the proposed methods are considered. The applicability of the presented results to the synthesis of test sequence generators with a given switching activity for the purpose of testing storage devices and the formation of controlled random test sequences is substantiated. The results of the practical implementation of address sequence generators are presented and their main characteristics are evaluated.

scholarly journals UHNVM: A Universal Heterogeneous Cache Design with Non-Volatile Memory

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1760
Author(s):  
Xiaochang Li ◽  
Zhengjun Zhai
Keyword(s):  
Scale Up ◽  
Main Memory ◽  
Storage Devices ◽  
Fine Grained ◽  
Non Volatile Memory ◽  
Application Data ◽  
Volatile Memory ◽  
Legacy Applications ◽  
Application Codes ◽  
Code Understanding

During the recent decades, non-volatile memory (NVM) has been anticipated to scale up the main memory size, improve the performance of applications, and reduce the speed gap between main memory and storage devices, while supporting persistent storage to cope with power outages. However, to fit NVM, all existing DRAM-based applications have to be rewritten by developers. Therefore, the developer must have a good understanding of targeted application codes, so as to manually distinguish and store data fit for NVM. In order to intelligently facilitate NVM deployment for existing legacy applications, we propose a universal heterogeneous cache hierarchy which is able to automatically select and store the appropriate data of applications for non-volatile memory (UHNVM), without compulsory code understanding. In this article, a program context (PC) technique is proposed in the user space to help UHNVM to classify data. Comparing to the conventional hot or cold files categories, the PC technique can categorize application data in a fine-grained manner, enabling us to store them either in NVM or SSDs efficiently for better performance. Our experimental results using a real Optane dual-inline-memory-module (DIMM) card show that our new heterogeneous architecture reduces elapsed times by about 11% compared to the conventional kernel memory configuration without NVM.

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

scholarly journals Ionic Liquid Electrolytes for Electrochemical Energy Storage Devices

Materials ◽  
2021 ◽  
Vol 14 (14) ◽  
pp. 4000
Author(s):  
Eunhwan Kim ◽  
Juyeon Han ◽  
Seokgyu Ryu ◽  
Youngkyu Choi ◽  
Jeeyoung Yoo
Keyword(s):  
Ionic Liquid ◽  
Energy Storage ◽  
Lithium Ion ◽  
Electrochemical Energy Storage ◽  
Storage Device ◽  
Energy Storage Device ◽  
Energy Storage Devices ◽  
Storage Devices ◽  
Storage Ability ◽  
Electrochemical Energy

For decades, improvements in electrolytes and electrodes have driven the development of electrochemical energy storage devices. Generally, electrodes and electrolytes should not be developed separately due to the importance of the interaction at their interface. The energy storage ability and safety of energy storage devices are in fact determined by the arrangement of ions and electrons between the electrode and the electrolyte. In this paper, the physicochemical and electrochemical properties of lithium-ion batteries and supercapacitors using ionic liquids (ILs) as an electrolyte are reviewed. Additionally, the energy storage device ILs developed over the last decade are introduced.

scholarly journals Layered double hydroxide membrane with high hydroxide conductivity and ion selectivity for energy storage device

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Jing Hu ◽  
Xiaomin Tang ◽  
Qing Dai ◽  
Zhiqiang Liu ◽  
Huamin Zhang ◽  
...  
Keyword(s):  
Energy Storage ◽  
High Performance ◽  
Ion Selectivity ◽  
Storage Device ◽  
Hydroxyl Groups ◽  
Flow Battery ◽  
Energy Storage Devices ◽  
Storage Devices ◽  
Ions Transport ◽  
Double Hydroxides

AbstractMembranes with fast and selective ions transport are highly demanded for energy storage devices. Layered double hydroxides (LDHs), bearing uniform interlayer galleries and abundant hydroxyl groups covalently bonded within two-dimensional (2D) host layers, make them superb candidates for high-performance membranes. However, related research on LDHs for ions separation is quite rare, especially the deep-going study on ions transport behavior in LDHs. Here, we report a LDHs-based composite membrane with fast and selective ions transport for flow battery application. The hydroxide ions transport through LDHs via vehicular (standard diffusion) & Grotthuss (proton hopping) mechanisms is uncovered. The LDHs-based membrane enables an alkaline zinc-based flow battery to operate at 200 mA cm−2, along with an energy efficiency of 82.36% for 400 cycles. This study offers an in-depth understanding of ions transport in LDHs and further inspires their applications in other energy-related devices.

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