scholarly journals A 30 μW Embedded Real-Time Cetacean Smart Detector

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 819
Author(s):  
Sebastián Marzetti ◽  
Valentin Gies ◽  
Paul Best ◽  
Valentin Barchasz ◽  
Sébastien Paris ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Data Storage ◽  
High Performance ◽  
Sampling Rate ◽  
Detection Accuracy ◽  
Sperm Whales ◽  
Recording Equipment ◽  
Battery Cell ◽  
Ultra Low Power

Cetacean monitoring is key to their protection. Understanding their behavior relies on multi-channel and high-sampling-rate underwater acoustic recordings for identifying and tracking them in a passive way. However, a lot of energy and data storage is required, requiring frequent human maintenance operations. To cope with these constraints, an ultra-low power mixed-signal always-on wake-up is proposed. Based on pulse-pattern analysis, it can be used for triggering a multi-channel high-performance recorder only when cetacean clicks are detected, thus increasing autonomy and saving storage space. This detector is implemented as a mixed architecture making the most of analog and digital primitives: this combination drastically improves power consumption by processing high-frequency data using analog features and lower-frequency ones in a digital way. Furthermore, a bioacoustic expert system is proposed for improving detection accuracy (in ultra-low-power) via state machines. Power consumption of the system is lower than 30 μW in always-on mode, allowing an autonomy of 2 years on a single CR2032 battery cell with a high detection accuracy. The receiver operating characteristic (ROC) curve obtained has an area under curve of 85% using expert rules and 75% without it. This implementation provides an excellent trade-off between detection accuracy and power consumption. Focused on sperm whales, it can be tuned to detect other species emitting pulse trains. This approach facilitates biodiversity studies, reducing maintenance operations and allowing the use of lighter, more compact and portable recording equipment, as large batteries are no longer required. Additionally, recording only useful data helps to reduce the dataset labeling time.

scholarly journals Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

VLSI Design ◽  
2009 ◽  
Vol 2009 ◽  
pp. 1-14 ◽  
Author(s):  
Ramesh Vaddi ◽  
S. Dasgupta ◽  
R. P. Agarwal
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
High Performance ◽  
Device Structure ◽  
Subthreshold Region ◽  
Ultra Low Power ◽  
Sensor Applications ◽  
Subthreshold Operation ◽  
Design Challenges

In recent years, subthreshold operation has gained a lot of attention due to ultra low-power consumption in applications requiring low to medium performance. It has also been shown that by optimizing the device structure, power consumption of digital subthreshold logic can be further minimized while improving its performance. Therefore, subthreshold circuit design is very promising for future ultra low-energy sensor applications as well as high-performance parallel processing. This paper deals with various device and circuit design challenges associated with the state of the art in optimal digital subthreshold circuit design and reviews device design methodologies and circuit topologies for optimal digital subthreshold operation. This paper identifies the suitable candidates for subthreshold operation at device and circuit levels for optimal subthreshold circuit design and provides an effective roadmap for digital designers interested to work with ultra low-power applications.

scholarly journals A 6-bit Low-Power High-Speed Flash ADC using 180 nm CMOS process

2014 ◽  
Vol 17 (1) ◽  
pp. 52-61
Author(s):  
Thanh Tri Vo ◽  
Trong Tu Bui ◽  
Duc Hung Le ◽  
Cong Kha Pham
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Sampling Rate ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Flash Adc ◽  
High Sampling Rate ◽  
Simulation Results

In this paper we present a design of Flash-ADC that can achieve high performance and low power consumption. By using the Double Sampling Rate technique and a new comparator topology with low kick-back noise, this design can achieve high sampling rate while still consuming low power. The design is implemented in a 0.18 m CMOS process. The simulation results show that this design can work at 400 MSps and power consumption is only 16.24 mW. The DNL and INL are 0.15 LSB and 0.6 LSB, respectively.

An Ultra-low Power Consumption MAC Protocol Complied with IEEE 802.15.4/4e for Wireless Smart Utility Networks

2016 ◽  
Vol 136 (11) ◽  
pp. 1555-1566 ◽  
Author(s):  
Jun Fujiwara ◽  
Hiroshi Harada ◽  
Takuya Kawata ◽  
Kentaro Sakamoto ◽  
Sota Tsuchiya ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Ieee 802.15.4 ◽  
Mac Protocol ◽  
Low Power Consumption ◽  
Ultra Low Power

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

scholarly journals Ultra Low Power Consumption for Self-Oscillating Nanoelectromechanical Systems Constructed by Contacting Two Nanowires

Nano Letters ◽  
2013 ◽  
Vol 13 (4) ◽  
pp. 1451-1456 ◽  
Author(s):  
T. Barois ◽  
A. Ayari ◽  
P. Vincent ◽  
S. Perisanu ◽  
P. Poncharal ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Nanoelectromechanical Systems ◽  
Low Power Consumption ◽  
Ultra Low Power

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals An Ultra-Low-Power K-Band 22.2 GHz-to-26.9 GHz Current-Reuse VCO Using Dynamic Back-Gate-Biasing Technique

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 889
Author(s):  
Xiaoying Deng ◽  
Peiqi Tan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Back Gate ◽  
Ultra Low Power ◽  
Current Reuse ◽  
K Band

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

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