An Efficient Genetic Encoding Scheme for Multiplierless Color Space Converter Design

2013 ◽  
Vol 284-287 ◽  
pp. 3015-3019
Author(s):  
Ching Yi Chen ◽  
Ching Han Chen ◽  
Chih Hao Ma ◽  
Po Yi Wu
Keyword(s):  
Video Compression ◽  
Video Processing ◽  
High Speed ◽  
Color Space ◽  
Low Complexity ◽  
Evolvable Hardware ◽  
Low Area ◽  
Design And Synthesis ◽  
Ycbcr Color Space ◽  
Field Programmable

Color space conversion has become a very important role in image and video processing systems. To speed up some processing processes, many communication and multimedia video compression schemes use luminance-chrominance type color spaces, such as YCbCr or YUV, making a mechanism for converting between different formats necessary. Therefore, techniques which efficiently implement this conversion are desired. For the recent years, a new field of research called Evolvable Hardware (EHW) has emerged which combines aspects of evolutionary computation with hardware design and synthesis. It is a new scheme inspired by natural evolution, for automatic design of hardware systems. This paper presents a novel evolutionary approach for efficient implementation of a RGB to YCbCr color space converter suitable for Field Programmable Gate Array (FPGAs) and VLSI. In the proposed method, we use the genetic algorithm to automatically evolve the multiplierless architecture of the color space converter. The architecture employs only a few shift and addition operations to replace the complex multiplications. The experimental results represent that the performance of implemented architecture is good at RGB to YCbCr color space converting, and it also has the advantages of high-speed, low-complexity, and low-area.

AUTOMATIC DESIGN OF SHIFT-AND-ADD BASED COLOR SPACE CONVERTER USING A GENETIC ALGORITHM

2013 ◽  
Vol 37 (3) ◽  
pp. 959-970
Author(s):  
Ching-Yi Chen ◽  
Ching-Han Chen ◽  
Chih-Hao Ma ◽  
Po-Yi Wu
Keyword(s):  
Genetic Algorithm ◽  
High Speed ◽  
Design Method ◽  
Color Space ◽  
Low Complexity ◽  
Automatic Design ◽  
Low Area ◽  
Color Space Conversion ◽  
Color Conversion ◽  
Novel Design

The main purpose of this paper is to investigate a novel design method using a genetic algorithm (GA) to automatically evolve the multiplierless CSC circuit architecture. In order to demonstrate the effectiveness of the described design method, several test images are adopted respectively to perform RGB to YCbCr color conversion experiment. The experimental results represent that the performance of the implemented hardware architecture is good when carrying out color space conversion from RGB to YCbCr. It also has the advantage of being high-speed, low-complexity, and low-area.

scholarly journals A High Speed Architecture for Lifting-based 2-D Cohen-Daubechies-Feauveau (5,3) Discrete Wavelet Transform used in JPEG2000

2017 ◽  
Vol 6 (1) ◽  
pp. 24 ◽  
Author(s):  
Mohammad Rafi Lone ◽  
Najeed- Ud-Din
Keyword(s):  
Real Time ◽  
Video Processing ◽  
High Speed ◽  
Parallel Implementation ◽  
Critical Path ◽  
Low Complexity ◽  
Discrete Wavelet ◽  
Throughput Optimization ◽  
Xilinx Fpga ◽  
Parallel Fashion

For real-time applications, efficient VLSI implementation of DWT is desired. In this paper, DWT architecture based on retiming for pipelining and unfolding is presented. The architecture is based on lifting one-dimensional Cohen-Daubechies-Feauveau (CDF) (5,3) wavelet filter, which is easily extended to 2-D implementation. It consists of low complexity and easily repeatable components. This paper is focused on the critical path minimization and throughput optimization at the same time. The architecture has been implemented on Virtex 6 Xilinx FPGA platform. The implementation results show that the critical path is minimized four to five times, while throughput is doubled, making the overall architecture approximately ten times faster when compared with the conventional lifting-based DWT architecture. Further with parallel implementation, the throughput has doubled without any increase in number of row buffers, implying that the architecture is memory efficient as well. The even and odd rows of the image are scanned in parallel fashion. To perform the 2-D DWT transform of an image of size 15 Megapixels, it takes 16.86 ms, which implies 59 images of that size can be processed in one second. This can be utilized for real-time video processing applications even for high resolution videos.

scholarly journals A Study of Automatic and Real-Time Table Tennis Fault Serve Detection System

Sports ◽  
2018 ◽  
Vol 6 (4) ◽  
pp. 158
Author(s):  
Chang-Hung Hung
Keyword(s):  
High Speed ◽  
Detection System ◽  
Color Space ◽  
Principal Component ◽  
Morphological Processing ◽  
Tennis Ball ◽  
Table Tennis ◽  
Ycbcr Color Space ◽  
Space Processing ◽  
Principal Component Pursuit

Calling a table tennis fault serve has never been easy for umpires, since they can only rely on their intuition. This study presents an algorithm that is able to automatically find the positions of the ball and racket in the images captured by high-speed camera. The trajectory of ball toss is analyzed and the result can be used as the objective basis for the umpire to decide if the serve is legal. This algorithm mainly consists of YCbCr color space processing, morphological processing method, circle Hough transform application, separation of moving and static components in an image sequence using the stable principal component pursuit method. The experiment results show that YCbCr color space provides better performance than HSV color space in recognizing the ball color close to skin tone. It is also demonstrated that the positions of the ball and racket can be successfully located by using the methods of color segmentation and stable principal component pursuit. Lastly, it is hoped that this study will provide more useful information regarding how to identify illegal ball toss in tennis ball game using image processing techniques to other researchers.

Accelerating Color Space Conversion Using CUDA-Enabled Graphic Processing Units

2013 ◽  
Vol 716 ◽  
pp. 505-509 ◽  
Author(s):  
Hang Jun Yang ◽  
Jian Wang ◽  
Xiao Yong Ji
Keyword(s):  
Video Compression ◽  
Video Processing ◽  
Multicore Processors ◽  
Color Space ◽  
Graphics Hardware ◽  
Functional Requirements ◽  
Graphic Processing Units ◽  
Color Space Conversion ◽  
Novel Approach ◽  
Software Implementations

Color space conversion (CSC) is an important kernel in the area of image and video processing applications including video compression. CSC is a compute-intensive time-consuming operation that consumes up to 40% of processing time of a highly optimised decoder. Several hardware and software implementations for CSC have been found. Hardware implementations can achieve a higher performance compared with software-only solutions. However, the flexibility of software solutions is desirable for various functional requirements and faster time to market. Multicore processors, especially programmable GPUs, provide an opportunity to increase the performance of CSC by exploiting data parallelism. In this paper, we present a novel approach for efficient implementation of color space conversion. The proposed approach has been implemented and verified using computed unified device architecture (CUDA) on graphics hardware. Our experiments results show that the speedup of up to17×can been obtained.

A Comparative Study of Color Space Conversion on Homogeneous and Heterogeneous Multicore

2014 ◽  
Vol 519-520 ◽  
pp. 724-728
Author(s):  
Chen Chu ◽  
Jian Wang ◽  
Sen Ke Hou ◽  
Qi Lv ◽  
Guo Qiang Ma ◽  
...  
Keyword(s):  
Video Compression ◽  
Video Processing ◽  
Processing Time ◽  
Multicore Processors ◽  
Color Space ◽  
Data Parallelism ◽  
Heterogeneous Multicore ◽  
Color Space Conversion ◽  
Image And Video Processing ◽  
Novel Approaches

Color space conversion (CSC) is an important kernel in the area of image and video processing applications including video compression. As a matrix math, this operation consumes up to 40% of processing time of a highly optimized decoder. Therefore, techniques which efficiently implement this conversion are desired. Multicore processors provide an opportunity to increase the performance of CSC by exploiting data parallelism. In this paper, we present three novel approaches for efficient implementation of color space conversion suitable for homogeneous and heterogeneous multicore. We compare the performance of color space conversion on a variety of platforms including OpenMP running on homogeneous multicore CPUs, CUDA with NVIDIA GPUs and OpenCL running on both NVIDIA and ATI GPUs. Our experimental results show that the speedup of3×, 17×and15×can been obtained, respectively.

scholarly journals Design of High Speed and Low Area Confined Multiplier on FPGA

2021 ◽  
Vol 11 (4) ◽  
pp. 2736-2746
Author(s):  
Kandagatla Ravi Kumar ◽  
Cheeli Priyadarshini ◽  
Kanakam Bhavani ◽  
Ankam Varun Sundar Kumar ◽  
Palanki Naga Nanda Sai
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Digital Signal ◽  
Low Area ◽  
Field Programmable ◽  
Dsp Applications ◽  
Advanced Applications ◽  
Main Factor

In this Advanced world, Technology is playing the major role. Most importantly development in Electronics field has a large impact on the improved life style. Among the advanced applications, DSP ranks first in place. Multipliers are the most basic elements that are widely used in the Digital Signal Processing (DSP) applications. Therefore, the design of the multiplier is the main factor for the performance of the device. Using RTL simulation and a Field Programmable Gate Array (FPGA), we compare the performance of a serial multiplier with an advanced multiplier. Many single bit adders are removed and replaced with multiplexers in this project. So that the less often used FPGAs are fully used by occupying fewer divisions and slices. The use of multiplier architecture results in significant reductions in FPGA resources, latency, area, and power. These multiplication approaches are created utilizing RTL simulation in Xilinx ISE simulator and synthesis in Xilinx ISE 14.7. Finally, the Spartan 3E FPGA is used to implement the design.

scholarly journals Design Space Exploration for High-Speed Implementation of the MISTY1 Block Cipher

2021 ◽  
Vol 2021 ◽  
pp. 1-14
Author(s):  
Raza Hasan ◽  
Yasir Khizar ◽  
Salman Mahmood ◽  
Muhammad Kashif Sheikh
Keyword(s):  
High Speed ◽  
Design Space Exploration ◽  
Block Cipher ◽  
Design Space ◽  
High Efficiency ◽  
Space Exploration ◽  
Wireless Applications ◽  
Low Area ◽  
Field Programmable ◽  
Very High

This paper proposes 2 × unrolled high-speed architectures of the MISTY1 block cipher for wireless applications including sensor networks and image encryption. Design space exploration is carried out for 8-round MISTY1 utilizing dual-edge trigger (DET) and single-edge trigger (SET) pipelines to analyze the tradeoff w.r.t. speed/area. The design is primarily based on the optimized implementation of lookup tables (LUTs) for MISTY1 and its core transformation functions. The LUTs are designed by logically formulating S9/S7 s-boxes and FI and {FO + 32-bit XOR} functions with the fine placement of pipelines. Highly efficient and high-speed MISTY1 architectures are thus obtained and implemented on the field-programmable gate array (FPGA), Virtex-7, XC7VX690T. The high-speed/very high-speed MISTY1 architectures acquire throughput values of 25.2/43 Gbps covering an area of 1331/1509 CLB slices, respectively. The proposed MISTY1 architecture outperforms all previous MISTY1 implementations indicating high speed with low area achieving high efficiency value. The proposed architecture had higher efficiency values than the existing AES and Camellia architectures. This signifies the optimizations made for proposed high-speed MISTY1 architectures.

scholarly journals A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 2023
Author(s):  
Thanikodi Manoj Kumar ◽  
Kasarla Satish Reddy ◽  
Stefano Rinaldi ◽  
Bidare Divakarachari Parameshachari ◽  
Kavitha Arunachalam
Keyword(s):  
Data Security ◽  
High Speed ◽  
Fpga Implementation ◽  
Digital Data ◽  
Low Area ◽  
Aes Algorithm ◽  
Field Programmable ◽  
Hardware Architectures ◽  
Cyber Crimes ◽  
The Look

Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the look up tables (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.

Modern Technology for Image processing and Computer vision -A Review

2018 ◽  
Vol 1 (2) ◽  
pp. 17-23
Author(s):  
Takialddin Al Smadi
Keyword(s):  
Image Processing ◽  
Computer Vision ◽  
Augmented Reality ◽  
Video Compression ◽  
Video Processing ◽  
Vision System ◽  
Citrus Fruit ◽  
Modern Technology ◽  
Image And Video Processing ◽  
Depth Video

This survey outlines the use of computer vision in Image and video processing in multidisciplinary applications; either in academia or industry, which are active in this field.The scope of this paper covers the theoretical and practical aspects in image and video processing in addition of computer vision, from essential research to evolution of application.In this paper a various subjects of image processing and computer vision will be demonstrated ,these subjects are spanned from the evolution of mobile augmented reality (MAR) applications, to augmented reality under 3D modeling and real time depth imaging, video processing algorithms will be discussed to get higher depth video compression, beside that in the field of mobile platform an automatic computer vision system for citrus fruit has been implemented ,where the Bayesian classification with Boundary Growing to detect the text in the video scene. Also the paper illustrates the usability of the handed interactive method to the portable projector based on augmented reality.   © 2018 JASET, International Scholars and Researchers Association

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