scholarly journals A Novel Architecture of Radix-3 Singlepath Delay Feedback (R3SDF) FFT Using MCSLA

2018 ◽  
Vol 10 (1) ◽  
pp. 37
Author(s):  
Periyarselvam K ◽  
Saravanakumar G ◽  
Anand M
Keyword(s):  
Power Consumption ◽  
Orthogonal Frequency Division Multiplexing ◽  
Digital Signal ◽  
Path Delay ◽  
Hardware Complexity ◽  
Large Power ◽  
Fft Processor ◽  
Novel Design ◽  
Multiplexing Systems ◽  
Single Path

Fast Fourier transform (FFT) is widely used in digital signal processing and telecommunications, particularly in orthogonal frequency division multiplexing systems, to overcome the problems associated with orthogonal subcarriers. A new algorithm of radix-3 FFT has been introduced in this work. The DFT of length N can be realized from three DFT sequences; each of length N/3.Radix-3 algorithm reduces the number of multiplications required for realizing DFT.A novel design of Radix-3pipelined Single path Delay Feedback (R3SDF) FFT using MCSLA has been proposed in this paper. First, the pipelined radix-3 SDF FFT method has been designed. It has less area and large power consumption and delay. In order to overcome these problems, modified carry select adder structure is used to perform the adder operation for reducing the power consumption and delay. Finally, the MCSLA is integrated into radix-3 SDF FFT processor. The hardware complexity and execution time for implementing radix-3 FFT algorithm can be reduced than other FFTs.

A Survey on FFT/IFFT Processors for Next Generation Telecommunication Systems

2017 ◽  
Vol 27 (03) ◽  
pp. 1830001 ◽  
Author(s):  
Elango Konguvel ◽  
Muniandi Kannan
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Orthogonal Frequency Division Multiplexing ◽  
High Speed ◽  
Digital Signal ◽  
Path Delay ◽  
Chip Design ◽  
Optical Ofdm ◽  
Processing Device ◽  
Single Path

The Fast Fourier Transform and Inverse Fast Fourier Transform (FFT/IFFT) are the most significant digital signal processing (DSP) techniques used in Orthogonal Frequency Division Multiplexing (OFDM)-based applications which include day-to-day wired/wireless communications, broadband access, and information sharing. The advancements in telecommunication technologies require an efficient FFT/IFFT processing device to meet the necessary specifications which depend on the particular application. A real-time implementation of high-speed FFT/IFFT processor with less area that operates in minimal power consumption is essential in designing an OFDM integrated chip. A comparative study of efficient algorithms and architectures for FFT chip design is presented in this paper. It is also recommended that mixed-radix/higher-radix algorithm combined with Single-path Delay Commutator (SDC) architecture is appropriate for massive MIMO in 5G, optical OFDM, cooperative MIMO and multi-user MIMO-based applications.

A Variable-Length FFT Processor Base on Mixed-Radix Algorithm for PAPR Reduction in OFDM Systems

2012 ◽  
Vol 588-589 ◽  
pp. 826-829
Author(s):  
Xiang Bin Meng ◽  
Jin Xiang Wang ◽  
Hai Long Yan
Keyword(s):  
Communication Systems ◽  
Orthogonal Frequency Division Multiplexing ◽  
Cmos Technology ◽  
Variable Length ◽  
Papr Reduction ◽  
Path Delay ◽  
Ofdm Systems ◽  
Pipeline Architecture ◽  
Fft Processor ◽  
Single Path

An attractive technique of variable-length Fast Fourier transform (FFT) processor is proposed for PAPR reduction in orthogonal frequency division multiplexing (OFDM) systems. Mixed-radix algorithm and single path delay feedback (SDF) pipeline architecture is adopted to obtain low computation complexity and preferable flexibility for its VLSI implementation. The FFT processor can be reconfigured as 512, 1024, 2048, 4096-points, moreover, the only one RAM unit is used for store sine/cosine tables. The chip is mapped to the 0.18 CMOS technology and the core area is 7.896mm2. The experiment results show that the proposed FFT processor is suitable for PAPR reduction in OFDM communication systems.

scholarly journals VLSI Implementation of Reconfigurable FFT Processor Using Vedic Mathematics

2015 ◽  
Vol 5 (2) ◽  
Author(s):  
Bharatha K. Babu ◽  
G. Nanthini
Keyword(s):  
Fourier Transform ◽  
Small Area ◽  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Path Delay ◽  
Vedic Mathematics ◽  
Fft Processor ◽  
Wide Range ◽  
Single Path

Fast Fourier transform has been used in wide range of applications such as digital signal processing and wireless communications. In this we present a implementation of reconfigurable FFT processor using single path delay feedback architecture. To eliminate the use of read only memory’s (ROM’S). These are used to store the twiddle factors. To achieve the ROM-less FFT processor the proposed architecture applies the bit parallel multipliers and reconfigurable complex multipliers, thus consuming less power. The proposed architecture, Reconfigurable FFT processor based on Vedic mathematics is designed, simulated and implemented using VIRTEX-5 FPGA. Urdhva Triyakbhyam algorithm is an ancient Vedic mathematic sutra, which is used to achieve the high performance. This reconfigurable DIF-FFT is having the high speed and small area as compared with other conventional DIF-FFT

scholarly journals Efficient-Scheduling Parallel Multiplier-Based Ring-LWE Cryptoprocessors

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 413 ◽  
Author(s):  
Tuy Nguyen Tan ◽  
Hanho Lee
Keyword(s):  
Field Programmable Gate Array ◽  
Path Delay ◽  
Hardware Complexity ◽  
Parallel Multiplier ◽  
Multiplication Operation ◽  
Encryption And Decryption ◽  
Field Programmable ◽  
Speed Up ◽  
Learning With Errors ◽  
Single Path

This paper presents a novel architecture for ring learning with errors (LWE) cryptoprocessors using an efficient approach in encryption and decryption operations. By scheduling multipliers to work in parallel, the encryption and decryption time are significantly reduced. In addition, polynomial multiplications are conducted using radix-2 and radix-8 multiple delay feedback (MDF) architecture-based number theoretic transform (NTT) multipliers to speed up the multiplication operation. To reduce the hardware complexity of an NTT multiplier, three bit-reverse operations during the NTT and inverse NTT (INTT) processes are removed. Polynomial additions in the ring-LWE encryption phase are also arranged to work simultaneously to reduce the latency. As a result, the proposed efficient-scheduling parallel multiplier-based ring-LWE cryptoprocessors can achieve higher throughput and efficiency compared with existing architectures. The proposed ring-LWE cryptoprocessors are synthesized and verified using Xilinx VIVADO on a Virtex-7 field programmable gate array (FPGA) board. With security parameters n = 512 and q = 12,289, the proposed cryptoprocessors using radix-2 single-path delay feedback (SDF), radix-2 MDF, and radix-8 MDF multipliers perform encryption in 4.58 μ s, 1.97 μ s, and 0.89 μ s, and decryption in 4.35 μ s, 1.82 μ s, and 0.71 μ s, respectively. A comparison of the obtained throughput and efficiency with those of previous studies proves that the proposed cryptoprocessors achieve a better performance.

scholarly journals Design and Implementation of N-Point FFT Processor for MIMO-OFDM Systems using Radix-N

2020 ◽  
Vol 9 (4) ◽  
pp. 1101-1104
Keyword(s):  
High Efficiency ◽  
Multiple Input Multiple Output ◽  
Path Delay ◽  
Ofdm Systems ◽  
High Data ◽  
Fft Processor ◽  
Data Rates ◽  
Input Multiple Output ◽  
Mimo Ofdm ◽  
Single Path

This paper presents Single-path Delay Feedback (SDF) architecture for implementing Fast Fourier Transform (FFT) for Multiple-Input Multiple-Output Orthogonal Frequency Division Frequency Multiplexing (MIMO-OFDM). The architecture of Single-path Delay Feedback and memory scheduling are the basic concepts used to implement the FFT processor with variable length. Depending on the SDF architecture, we implement the FFT processor-based design which is proposed in this paper. In this paper, we use MIMOOFDM high data rates, high efficiency and high throughput. In this paper, we use radix-4 algorithm to implement the sequence because the speed of the operation is high. The functionality verification and the synthesis are carried out by using XLINIX.14.2.

scholarly journals VLSI Architecture of High Performance Multiplier for High Speed Applications

2020 ◽  
Vol 9 (3) ◽  
pp. 442-445
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Vlsi Architecture ◽  
Digital Signal ◽  
Full Adder ◽  
Vital Role ◽  
Path Delay

In the application of digital signal process multipliers play a vital role. With advances in technology, several researchers have tried and try to design multipliers which supply high speed, low power consumption, regularity of layout and thus less space or maybe combination of them in one multiplier factor. Thus, Compact VLSI design for four bit multiplier factor is planned during this paper that is appropriate for low power and high speed applications. Multiplier factor with high performance is achieved through the novel style of hybrid single bit full adder and Dadda algorithmic rule. The important path delay and power consumption of the planned multiplier factor square measure reduced by 65.9% and 24.5% severally when put next with existing multipliers. The planned multiplier factor is synthesized exploitation CADENCE five.1.0 EDA tool and simulated exploitation spectre virtuoso.

Hardware-Efficient Bartlett Spectral Density Estimator Based on Optimized R22FFT Processor Using CCSSI Method

2020 ◽  
pp. 2150023
Author(s):  
Abdolvahab Khalili Sadaghiani ◽  
Samad Sheikhaei
Keyword(s):  
Spectral Density ◽  
Low Power ◽  
Performance Comparison ◽  
Density Estimator ◽  
Path Delay ◽  
Fft Processor ◽  
Power Spectral ◽  
Coordinate Rotation ◽  
Psd Estimation ◽  
Single Path

This paper offers a novel, low-power, hardware-efficient, yet high-frequency architecture for a power spectral density (PSD) estimator, based on the Bartlett method, for low-power biomedical applications. The Bartlett method is a nonparametric method for PSD estimation. The proposed architecture operates based on a modified multiplierless 64-point optimized radix-22 single-path delay feedback (R22SDF) FFT processor. To obtain the final result, it also uses modified safe-scaling in a way that removes the need to use several extra hardware units. It takes advantage of combined coefficient selection and shift-and-add implementation (CCSSI) for computing twiddle factors which is a new algorithm based on digital computer coordinate rotation (CORDIC) for generating trigonometric values. The proposed method has the capability of operating on short word lengths (WLs). Artix-7 is the FPGA used in this research and Verilog is the language used for hardware design. For 8-bit WL and 244-mW power, a frequency of 286 MHz has been achieved. Several vital signals are used for performance comparison of the proposed technique with state-of-the-art designs.

scholarly journals Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 231
Author(s):  
Chester Sungchung Park ◽  
Sunwoo Kim ◽  
Jooho Wang ◽  
Sungkyung Park
Keyword(s):  
Integrated Circuit ◽  
Building Block ◽  
Orthogonal Frequency Division Multiplexing ◽  
Critical Path ◽  
Phase Error ◽  
System Level ◽  
Comb Filter ◽  
Carrier Aggregation ◽  
Path Delay ◽  
Front End

A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

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