scholarly journals CMOS RF Transmitters with On-Chip Antenna for Passive RFID and IoT Nodes

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1448 ◽  
Author(s):  
Massimo Merenda ◽  
Demetrio Iero ◽  
Francesco G. Della Corte
Keyword(s):  
Average Power ◽  
Monolithically Integrated ◽  
Rf Transmitters ◽  
Sufficient Power ◽  
Average Power Consumption ◽  
On Chip Antenna ◽  
Data Transmission System ◽  
On Chip ◽  
Loop Antennas ◽  
Passive Rfid

The performances of two RF transmitters, monolithically integrated with their antennas on a single CMOS microchip fabricated in a standard 0.35 µm process, are presented. The usage of these architectures in the Internet of Things (IoT) paradigm is envisioned, as part of a custom conceived data transmission system. The implemented circuits use two different directly on–off keying (OOK) modulated oscillator topologies whose outputs are employed to feed two loop antennas. The powering of both transmitters is duty-cycled for reducing the average power consumption to a few tenths of a microwatt, allowing the usage as low-power transmitters for IoT nodes. The integrated loop antennas radiate sufficient power for a few meters’ communication range. The OOK transmitted signal can be easily detected using a commercial receiver.

scholarly journals A Scatter-and-Gather Spiking Convolutional Neural Network on a Reconfigurable Neuromorphic Hardware

2021 ◽  
Vol 15 ◽  
Author(s):  
Chenglong Zou ◽  
Xiaoxin Cui ◽  
Yisong Kuang ◽  
Kefei Liu ◽  
Yuan Wang ◽  
...  
Keyword(s):  
Neural Networks ◽  
Large Scale ◽  
Average Power ◽  
Time Step ◽  
Mapping Algorithm ◽  
Learning Tasks ◽  
Main Challenge ◽  
Neuromorphic Hardware ◽  
Average Power Consumption ◽  
On Chip

Artificial neural networks (ANNs), like convolutional neural networks (CNNs), have achieved the state-of-the-art results for many machine learning tasks. However, inference with large-scale full-precision CNNs must cause substantial energy consumption and memory occupation, which seriously hinders their deployment on mobile and embedded systems. Highly inspired from biological brain, spiking neural networks (SNNs) are emerging as new solutions because of natural superiority in brain-like learning and great energy efficiency with event-driven communication and computation. Nevertheless, training a deep SNN remains a main challenge and there is usually a big accuracy gap between ANNs and SNNs. In this paper, we introduce a hardware-friendly conversion algorithm called “scatter-and-gather” to convert quantized ANNs to lossless SNNs, where neurons are connected with ternary {−1,0,1} synaptic weights. Each spiking neuron is stateless and more like original McCulloch and Pitts model, because it fires at most one spike and need be reset at each time step. Furthermore, we develop an incremental mapping framework to demonstrate efficient network deployments on a reconfigurable neuromorphic chip. Experimental results show our spiking LeNet on MNIST and VGG-Net on CIFAR-10 datasetobtain 99.37% and 91.91% classification accuracy, respectively. Besides, the presented mapping algorithm manages network deployment on our neuromorphic chip with maximum resource efficiency and excellent flexibility. Our four-spike LeNet and VGG-Net on chip can achieve respective real-time inference speed of 0.38 ms/image, 3.24 ms/image, and an average power consumption of 0.28 mJ/image and 2.3 mJ/image at 0.9 V, 252 MHz, which is nearly two orders of magnitude more efficient than traditional GPUs.

A Monolithically Integrated On-Chip Antenna in 0.18 $\mu$ m Standard CMOS Technology for Far-Field Short-Range Wireless Powering

2010 ◽  
Vol 9 ◽  
pp. 631-633 ◽  
Author(s):  
Soheil Radiom ◽  
Karim Mohammadpour-Aghdam ◽  
Guy A. E. Vandenbosch ◽  
Georges Gielen
Keyword(s):  
Short Range ◽  
Cmos Technology ◽  
Far Field ◽  
Monolithically Integrated ◽  
Wireless Powering ◽  
On Chip Antenna ◽  
On Chip

scholarly journals High-Speed Serializer for a 64 GS s<sup>−1</sup> Digital-to-Analog Converter in a 28 nm Fully-Depleted Silicon-on-Insulator CMOS Technology

2018 ◽  
Vol 16 ◽  
pp. 99-108
Author(s):  
Daniel Widmann ◽  
Markus Grözing ◽  
Manfred Berroth
Keyword(s):  
High Speed ◽  
Average Power ◽  
Silicon On Insulator ◽  
Output Stage ◽  
Fully Depleted ◽  
Data Rates ◽  
Average Power Consumption ◽  
Digital To Analog ◽  
On Chip ◽  
28 Nm

Abstract. An attractive solution to provide several channels with very high data rates of tens of Gbit s−1 for digital-to-analog converters (DACs) in arbitrary waveform generators (AWGs) is to use a high speed serializer in front of the DAC. As data sources, on-chip memories, digital signal processors or field-programmable gate arrays can be used. Here, we present a serializer consisting of a 19 channel 16:1 multiplexer (MUX) for output data rates up to 64 Gbit s−1 per channel and a low skew (∼ 8.8 ps) two-phase frequency divider and clock distribution network that is completely realized in static CMOS logic. The circuit is designed in a 28 nm Fully-Depleted Silicon-on-Insulator (FD-SOI) technology and will be used in an 8 bit 64 GS s−1 DAC between the on-chip memory and the DAC output stage. Due to a four bits unary and four bits binary segmentation, a 19 channel MUX is required. Simulations on layout level reveal a data-dependent peak-to-peak jitter of less than 1.8 ps at the output of one MUX channel with a total average power consumption of approximately 1.15 W of the whole MUX and clock network.

Power analysis approach and its application to IP-based SoC design

2016 ◽  
Vol 35 (3) ◽  
Author(s):  
Yaseer Arafat Durrani ◽  
Teresa Riesgo ◽  
Muhammad Imran Khan ◽  
Tariq Mahmood
Keyword(s):  
Power Consumption ◽  
Design Methodology ◽  
Average Power ◽  
Power Estimation ◽  
Statistical Characteristics ◽  
Estimation Accuracy ◽  
Average Error ◽  
Average Power Consumption ◽  
On Chip ◽  
Practical Implications

Purpose Low-power consumption has become an important issue that cannot be ignored in System-on-Chip (SoC) design. The key challenge encountered by system design is how to maintain balance between the estimation accuracy and speed. This paper aims at demonstrating an accurate and fast power estimation technique. Design/methodology/approach The methodology adopted in the paper is to use input patterns with the predefined statistical characteristics which helps to analyze the average power consumption of the different intellectual-property (IP) cores and the interconnects/buses in SoC design. Similarly the paper has implemented Genetic algorithm (GA) to generate sequences of input signals during the power estimation procedure. Findings The GA concurrently optimizes the input signal characteristics that influence the final solution of the pattern. In addition to that, a Monte-Carlo zero-delay simulation is also performed for individual IP core and bus at high-level. By the simple addition of these cores/buses, power is predicted by a novel macro-model function. In experiments, the average error is estimated at 13.84%. Research limitations/implications To present the research findings with clarity and to avoid complexities, the paper does not consider delay factors like glitches, jitter etc. in the power model. Practical implications The proposed methodology allowed accurate power/energy analysis of practical applications mapped onto Network-on-Chip (NoC) based Multiprocessors SoC platform. It enables the performance analysis of different design alternatives under the load imposed by complex applications. Originality/value This paper is an original contribution and the results demonstrate that our novel technique could be implemented to achieve fast and accurate power estimation in the early stage of any SoC design.

Monolithically-Integrated Millimetre-Wave Wavelet Transmitter With On-Chip Antenna

2014 ◽  
Vol 24 (9) ◽  
pp. 625-627 ◽  
Author(s):  
Lars Ohlsson ◽  
Tomas Bryllert ◽  
Daniel Sjoberg ◽  
Lars-Erik Wernersson
Keyword(s):  
Millimetre Wave ◽  
Monolithically Integrated ◽  
On Chip Antenna ◽  
On Chip

scholarly journals An Energy Efficient Thermally Regulated Optical Spectroscopy Cell for Lab-on-Chip Devices: Applied to Nitrate Detection

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 861
Author(s):  
Benjamin J. Murphy ◽  
Edward A. Luy ◽  
Katerina L. Panzica ◽  
Gregory Johnson ◽  
Vincent J. Sieben
Keyword(s):  
Energy Use ◽  
Limit Of Detection ◽  
Average Power ◽  
Griess Reagent ◽  
Optical Cell ◽  
Lab On Chip ◽  
Average Power Consumption ◽  
On Chip ◽  
Air Pockets ◽  
20 Nm

Reagent-based colorimetric analyzers often heat the fluid under analysis for improved reaction kinetics, whilst also aiming to minimize energy use per measurement. Here, a novel method of conserving heat energy on such microfluidic systems is presented. Our design reduces heat transfer to the environment by surrounding the heated optical cell on four sides with integral air pockets, thereby realizing an insulated and suspended bridge structure. Our design was simulated in COMSOL Multiphysics and verified in a polymethyl methacrylate (PMMA) device. We evaluate the effectiveness of the insulated design by comparing it to a non-insulated cell. For temperatures up to 55 °C, the average power consumption was reduced by 49.3% in the simulation and 40.2% in the experiment. The designs were then characterized with the vanadium and Griess reagent assay for nitrate at 35 °C. Nitrate concentrations from 0.25 µM to 50 µM were tested and yielded the expected linear relationship with a limit of detection of 20 nM. We show a reduction in energy consumption from 195 J to 119 J per 10 min measurement using only 4 µL of fluid. Efficient heating on-chip will have broad applicability to numerous colorimetric assays.

scholarly journals Improved Simulated Annealing Genetic Algorithm based Low power mapping for 3D NoC

2018 ◽  
Vol 232 ◽  
pp. 02022 ◽  
Author(s):  
Hanna He ◽  
Fang Fang ◽  
Wei Wang
Keyword(s):  
Genetic Algorithm ◽  
Simulated Annealing ◽  
Power Consumption ◽  
Average Power ◽  
Optimal Solution ◽  
Initial Population ◽  
Good Convergence ◽  
Average Power Consumption ◽  
Ip Cores ◽  
On Chip

Mapping of IP(Intellectual Property) cores onto NoC(Network-on-Chip) architectures is a key step in NoCbased designs. Energy is the key parameter to measure the designs. Therefore, we propose an Improved Simulated Annealing Genetic Alogrithm, abbreviated as ISAGA. The algorithm combines the parallelism of Genetic Algorithm(GA) and the local search ability of Simulated Annealing(SA). We improve the initial population selection of GA to get the lower power consumption mapping scheme. The experimental results show that compared with the GA, ISAGA has good convergence and can search the optimal solution quickly, which can effectively reduce the power consumption of the system. In the case of 124 IP cores, the average power consumption of the ISAGA is reduced by 32.0% compared with the GA.

CMOS fully-integrated wireless temperature sensors with on-chip antenna

2009 ◽  
Author(s):  
Fabio Aquilino ◽  
Francesco G. Della Corte ◽  
Letizia Fragomeni ◽  
Massimo Merenda ◽  
Fabio Zito
Keyword(s):  
Temperature Sensors ◽  
Fully Integrated ◽  
On Chip Antenna ◽  
On Chip
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