scholarly journals An Energy Efficient Thermally Regulated Optical Spectroscopy Cell for Lab-on-Chip Devices: Applied to Nitrate Detection

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 861
Author(s):  
Benjamin J. Murphy ◽  
Edward A. Luy ◽  
Katerina L. Panzica ◽  
Gregory Johnson ◽  
Vincent J. Sieben
Keyword(s):  
Energy Use ◽  
Limit Of Detection ◽  
Average Power ◽  
Griess Reagent ◽  
Optical Cell ◽  
Lab On Chip ◽  
Average Power Consumption ◽  
On Chip ◽  
Air Pockets ◽  
20 Nm

Reagent-based colorimetric analyzers often heat the fluid under analysis for improved reaction kinetics, whilst also aiming to minimize energy use per measurement. Here, a novel method of conserving heat energy on such microfluidic systems is presented. Our design reduces heat transfer to the environment by surrounding the heated optical cell on four sides with integral air pockets, thereby realizing an insulated and suspended bridge structure. Our design was simulated in COMSOL Multiphysics and verified in a polymethyl methacrylate (PMMA) device. We evaluate the effectiveness of the insulated design by comparing it to a non-insulated cell. For temperatures up to 55 °C, the average power consumption was reduced by 49.3% in the simulation and 40.2% in the experiment. The designs were then characterized with the vanadium and Griess reagent assay for nitrate at 35 °C. Nitrate concentrations from 0.25 µM to 50 µM were tested and yielded the expected linear relationship with a limit of detection of 20 nM. We show a reduction in energy consumption from 195 J to 119 J per 10 min measurement using only 4 µL of fluid. Efficient heating on-chip will have broad applicability to numerous colorimetric assays.

scholarly journals Development of a Pharmacogenetic Lab-on-Chip Assay Based on the In-Check Technology to Screen for Genetic Variations Associated to Adverse Drug Reactions to Common Chemotherapeutic Agents

Biosensors ◽  
2020 ◽  
Vol 10 (12) ◽  
pp. 202
Author(s):  
Rosario Iemmolo ◽  
Valentina La Cognata ◽  
Giovanna Morello ◽  
Maria Guarnaccia ◽  
Mariamena Arbitrio ◽  
...  
Keyword(s):  
Genetic Polymorphisms ◽  
Adverse Drug Reactions ◽  
Limit Of Detection ◽  
Chemotherapeutic Agents ◽  
Clinical Diagnostics ◽  
Individual Risk ◽  
Chip Assay ◽  
Drug Reactions ◽  
Lab On Chip ◽  
On Chip

Background: Antineoplastic agents represent the most common class of drugs causing Adverse Drug Reactions (ADRs). Mutant alleles of genes coding for drug-metabolizing enzymes are the best studied individual risk factors for these ADRs. Although the correlation between genetic polymorphisms and ADRs is well-known, pharmacogenetic tests are limited to centralized laboratories with expensive or dedicated instrumentation used by specialized personnel. Nowadays, DNA chips have overcome the major limitations in terms of sensibility, specificity or small molecular detection, allowing the simultaneous detection of several genetic polymorphisms with time and costs-effective advantages. In this work, we describe the design of a novel silicon-based lab-on-chip assay able to perform low-density and high-resolution multi-assay analysis (amplification and hybridization reactions) on the In-Check platform. Methods: The novel lab-on-chip was used to screen 17 allelic variants of three genes associated with adverse reactions to common chemotherapeutic agents: DPYD (Dihydropyrimidine dehydrogenase), MTHFR (5,10-Methylenetetrahydrofolate reductase) and TPMT (Thiopurine S-methyltransferase). Results: Inter- and intra assay variability were performed to assess the specificity and sensibility of the chip. Linear regression was used to assess the optimal hybridization temperature set at 52 °C (R2 ≈ 0.97). Limit of detection was 50 nM. Conclusions: The high performance in terms of sensibility and specificity of this lab-on-chip supports its further translation to clinical diagnostics, where it may effectively promote precision medicine.

scholarly journals A Scatter-and-Gather Spiking Convolutional Neural Network on a Reconfigurable Neuromorphic Hardware

2021 ◽  
Vol 15 ◽  
Author(s):  
Chenglong Zou ◽  
Xiaoxin Cui ◽  
Yisong Kuang ◽  
Kefei Liu ◽  
Yuan Wang ◽  
...  
Keyword(s):  
Neural Networks ◽  
Large Scale ◽  
Average Power ◽  
Time Step ◽  
Mapping Algorithm ◽  
Learning Tasks ◽  
Main Challenge ◽  
Neuromorphic Hardware ◽  
Average Power Consumption ◽  
On Chip

Artificial neural networks (ANNs), like convolutional neural networks (CNNs), have achieved the state-of-the-art results for many machine learning tasks. However, inference with large-scale full-precision CNNs must cause substantial energy consumption and memory occupation, which seriously hinders their deployment on mobile and embedded systems. Highly inspired from biological brain, spiking neural networks (SNNs) are emerging as new solutions because of natural superiority in brain-like learning and great energy efficiency with event-driven communication and computation. Nevertheless, training a deep SNN remains a main challenge and there is usually a big accuracy gap between ANNs and SNNs. In this paper, we introduce a hardware-friendly conversion algorithm called “scatter-and-gather” to convert quantized ANNs to lossless SNNs, where neurons are connected with ternary {−1,0,1} synaptic weights. Each spiking neuron is stateless and more like original McCulloch and Pitts model, because it fires at most one spike and need be reset at each time step. Furthermore, we develop an incremental mapping framework to demonstrate efficient network deployments on a reconfigurable neuromorphic chip. Experimental results show our spiking LeNet on MNIST and VGG-Net on CIFAR-10 datasetobtain 99.37% and 91.91% classification accuracy, respectively. Besides, the presented mapping algorithm manages network deployment on our neuromorphic chip with maximum resource efficiency and excellent flexibility. Our four-spike LeNet and VGG-Net on chip can achieve respective real-time inference speed of 0.38 ms/image, 3.24 ms/image, and an average power consumption of 0.28 mJ/image and 2.3 mJ/image at 0.9 V, 252 MHz, which is nearly two orders of magnitude more efficient than traditional GPUs.

scholarly journals CMOS RF Transmitters with On-Chip Antenna for Passive RFID and IoT Nodes

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1448 ◽  
Author(s):  
Massimo Merenda ◽  
Demetrio Iero ◽  
Francesco G. Della Corte
Keyword(s):  
Average Power ◽  
Monolithically Integrated ◽  
Rf Transmitters ◽  
Sufficient Power ◽  
Average Power Consumption ◽  
On Chip Antenna ◽  
Data Transmission System ◽  
On Chip ◽  
Loop Antennas ◽  
Passive Rfid

The performances of two RF transmitters, monolithically integrated with their antennas on a single CMOS microchip fabricated in a standard 0.35 µm process, are presented. The usage of these architectures in the Internet of Things (IoT) paradigm is envisioned, as part of a custom conceived data transmission system. The implemented circuits use two different directly on–off keying (OOK) modulated oscillator topologies whose outputs are employed to feed two loop antennas. The powering of both transmitters is duty-cycled for reducing the average power consumption to a few tenths of a microwatt, allowing the usage as low-power transmitters for IoT nodes. The integrated loop antennas radiate sufficient power for a few meters’ communication range. The OOK transmitted signal can be easily detected using a commercial receiver.

Microelectrode Design for Particle Trapping on Bioanalysis Platform

2015 ◽  
Vol 1115 ◽  
pp. 543-548 ◽  
Author(s):  
Siti Noorjannah Ibrahim ◽  
Maan M. Alkaisi
Keyword(s):  
Polystyrene Latex ◽  
Simulation Studies ◽  
Particle Trapping ◽  
Metal Insulator ◽  
Lab On Chip ◽  
Finite Element Software ◽  
Nickel Chromium ◽  
Metal Insulator Metal ◽  
On Chip ◽  
20 Nm

Microelectrode geometry has significant influence on particles trapping techniques used on bioanalysis platforms. In this paper, the particle trapping patterns of dipole, quadrupole and octupole microelectrode using dielectrophoretic force (DEP) are discussed. The microelectrodes were constructed on a metal-insulator-metal platform, built on a silicon nitride (Si3N4) coated silicon substrate. The back contact is made from 20 nm nickel-chromium (NiCr) and 100 nm gold (Au) as the first layer. Then, SU-8-2005 (negative photoresist) is used on the second layer to create microcavities for trapping the particles. The third layer, where the three geometries were patterned, is made from 20 nm NiCr and 100 nm Au layers. Prior to fabrication, the particles trapping patterns of the microelectrodes were profiled using a finite element software, COMSOL 3.5a. Trapping patterns for the three geometries were evaluated using polystyrene latex microbeads. Results from the experiment validate simulation studies in term of microelectrode trapping ability up to single particle efficiency. It provides the potential of converting the trapping platform into a lab-on-chip system.

scholarly journals A handheld point-of-care system for rapid detection of SARS-CoV-2 in under 20 minutes

2020 ◽  
Author(s):  
Jesus Rodriguez-Manzano ◽  
Kenny Malpartida-Cardenas ◽  
Nicolas Moser ◽  
Ivana Pennisi ◽  
Matthew Cavuto ◽  
...  
Keyword(s):  
Real Time ◽  
Limit Of Detection ◽  
Point Of Care ◽  
Lamp Assay ◽  
High Rate ◽  
Epidemiological Surveillance ◽  
Clinical Samples ◽  
Lab On Chip ◽  
Point Of Care System ◽  
On Chip

AbstractThe COVID-19 pandemic is a global health emergency characterized by the high rate of transmission and ongoing increase of cases globally. Rapid point-of-care (PoC) diagnostics to detect the causative virus, SARS-CoV-2, are urgently needed to identify and isolate patients, contain its spread and guide clinical management. In this work, we report the development of a rapid PoC diagnostic test (< 20 min) based on reverse transcriptase loop-mediated isothermal amplification (RT-LAMP) and semiconductor technology for the detection of SARS-CoV-2 from extracted RNA samples. The developed LAMP assay was tested on a real-time benchtop instrument (RT-qLAMP) showing a lower limit of detection of 10 RNA copies per reaction. It was validated against 183 clinical samples including 127 positive samples (screened by the CDC RT-qPCR assay). Results showed 90.55% sensitivity and 100% specificity when compared to RT-qPCR and average positive detection times of 15.45 ± 4.43 min. For validating the incorporation of the RT-LAMP assay onto our PoC platform (RT-eLAMP), a subset of samples was tested (n=40), showing average detection times of 12.89 ± 2.59 min for positive samples (n=34), demonstrating a comparable performance to a benchtop commercial instrument. Paired with a smartphone for results visualization and geo-localization, this portable diagnostic platform with secure cloud connectivity will enable real-time case identification and epidemiological surveillance.One Sentence SummaryWe demonstrate isothermal detection of SARS-CoV-2 in under 20 minutes from extracted RNA samples with a handheld Lab-on-Chip platform.

scholarly journals Design and Analysis of Silicon Nanowire FET for the Detection of Cardiac Troponin I Biomarker

2021 ◽  
Author(s):  
Shaik Ahmadsaidulu ◽  
B. Vamsi Krsihna ◽  
B V V Satyanarayana ◽  
Durga Prakash Matta
Keyword(s):  
Cardiac Troponin ◽  
Troponin I ◽  
Limit Of Detection ◽  
Human Life ◽  
Silicon Nanowire ◽  
Drain Current ◽  
Cardiac Troponin I ◽  
Lab On Chip ◽  
Immobilized Antibodies ◽  
On Chip

Abstract Cardiac arrests are one of the major health problems in present days. Cardiac Troponin-I (cTnI) is one of the important enzymes that causes cardiac arrest. Early diagnosis and proper medication of this saves human life. One of the prominent devices to diagnose troponin I is FET based bio-sensor. Normally, for these sensors’ higher sensitivities will be obtained as these biosensors structure consists of nanowire FETs. Proper selection of materials, dimensions, and doping concentrations of nanowire FET imply the perfection of a nanowire FET-based biosensor. In this work, Silicon Nanowire (SiNW) FET sensor is designed and simulated using COMSOL Multiphysics. Through this design, Identified the presence of different concentrations of cTnI present in human blood. The presence of different enzymes like cTnT, cTnI etc., bring changes in characteristics of SiNW FET sensor. With these changes in characteristics, we can identify the presence of these enzymes of a lower concentration also. The lower concentrations of these biomarkers will bring notable changes in the drain current. The characteristics were analysed with the SiNW FET which is equipped with immobilized antibodies on it. The considerable changes observed in these characteristics of FET sensor identifies the presence of cTnI biomarker and are attached to the monoclonal Antibodies (mAb). Our observations shown that the properties of designed SiNW FET changes with presence of these bio marker materials and a limit of detection is obtained the order of 2pg/mL. with further the design bio sensor with SiNW FET can be used for microfluidic and Lab-on-Chip applications also.

scholarly journals High-Speed Serializer for a 64 GS s<sup>−1</sup> Digital-to-Analog Converter in a 28 nm Fully-Depleted Silicon-on-Insulator CMOS Technology

2018 ◽  
Vol 16 ◽  
pp. 99-108
Author(s):  
Daniel Widmann ◽  
Markus Grözing ◽  
Manfred Berroth
Keyword(s):  
High Speed ◽  
Average Power ◽  
Silicon On Insulator ◽  
Output Stage ◽  
Fully Depleted ◽  
Data Rates ◽  
Average Power Consumption ◽  
Digital To Analog ◽  
On Chip ◽  
28 Nm

Abstract. An attractive solution to provide several channels with very high data rates of tens of Gbit s−1 for digital-to-analog converters (DACs) in arbitrary waveform generators (AWGs) is to use a high speed serializer in front of the DAC. As data sources, on-chip memories, digital signal processors or field-programmable gate arrays can be used. Here, we present a serializer consisting of a 19 channel 16:1 multiplexer (MUX) for output data rates up to 64 Gbit s−1 per channel and a low skew (∼ 8.8 ps) two-phase frequency divider and clock distribution network that is completely realized in static CMOS logic. The circuit is designed in a 28 nm Fully-Depleted Silicon-on-Insulator (FD-SOI) technology and will be used in an 8 bit 64 GS s−1 DAC between the on-chip memory and the DAC output stage. Due to a four bits unary and four bits binary segmentation, a 19 channel MUX is required. Simulations on layout level reveal a data-dependent peak-to-peak jitter of less than 1.8 ps at the output of one MUX channel with a total average power consumption of approximately 1.15 W of the whole MUX and clock network.

An efficient technique for the reduction of wavelength noise in resonance-based integrated photonic sensors

The Analyst ◽  
2014 ◽  
Vol 139 (22) ◽  
pp. 5901-5910 ◽  
Author(s):  
Farshid Ghasemi ◽  
Maysamreza Chamanzar ◽  
Ali A. Eftekhar ◽  
Ali Adibi
Keyword(s):  
Systematic Study ◽  
Limit Of Detection ◽  
Efficient Technique ◽  
Lab On Chip ◽  
Silicon Photonic ◽  
Photonic Sensors ◽  
On Chip

A systematic study of the limit of detection (LOD) in resonance-based silicon photonic lab-on-chip sensors is presented.

scholarly journals A customizable, low-power, wireless, embedded sensing platform for resistive nanoscale sensors

2022 ◽  
Vol 8 (1) ◽  
Author(s):  
Stefan Nedelcu ◽  
Kishan Thodkar ◽  
Christofer Hierold
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Limit Of Detection ◽  
Sampling Rate ◽  
Average Power ◽  
Physical Parameters ◽  
Embedded Sensing ◽  
Sensing Applications ◽  
Measurement Protocol ◽  
Average Power Consumption

AbstractCustomizable, portable, battery-operated, wireless platforms for interfacing high-sensitivity nanoscale sensors are a means to improve spatiotemporal measurement coverage of physical parameters. Such a platform can enable the expansion of IoT for environmental and lifestyle applications. Here we report a platform capable of acquiring currents ranging from 1.5 nA to 7.2 µA full-scale with 20-bit resolution and variable sampling rates of up to 3.125 kSPS. In addition, it features a bipolar voltage programmable in the range of −10 V to +5 V with a 3.65 mV resolution. A Finite State Machine steers the system by executing a set of embedded functions. The FSM allows for dynamic, customized adjustments of the nanosensor bias, including elevated bias schemes for self-heating, measurement range, bandwidth, sampling rate, and measurement time intervals. Furthermore, it enables data logging on external memory (SD card) and data transmission over a Bluetooth low energy connection. The average power consumption of the platform is 64.5 mW for a measurement protocol of three samples per second, including a BLE advertisement of a 0 dBm transmission power. A state-of-the-art (SoA) application of the platform performance using a CNT nanosensor, exposed to NO2 gas concentrations from 200 ppb down to 1 ppb, has been demonstrated. Although sensor signals are measured for NO2 concentrations of 1 ppb, the 3σ limit of detection (LOD) of 23 ppb is determined (1σ: 7 ppb) in slope detection mode, including the sensor signal variations in repeated measurements. The platform’s wide current range and high versatility make it suitable for signal acquisition from resistive nanosensors such as silicon nanowires, carbon nanotubes, graphene, and other 2D materials. Along with its overall low power consumption, the proposed platform is highly suitable for various sensing applications within the context of IoT.

Power analysis approach and its application to IP-based SoC design

2016 ◽  
Vol 35 (3) ◽  
Author(s):  
Yaseer Arafat Durrani ◽  
Teresa Riesgo ◽  
Muhammad Imran Khan ◽  
Tariq Mahmood
Keyword(s):  
Power Consumption ◽  
Design Methodology ◽  
Average Power ◽  
Power Estimation ◽  
Statistical Characteristics ◽  
Estimation Accuracy ◽  
Average Error ◽  
Average Power Consumption ◽  
On Chip ◽  
Practical Implications

Purpose Low-power consumption has become an important issue that cannot be ignored in System-on-Chip (SoC) design. The key challenge encountered by system design is how to maintain balance between the estimation accuracy and speed. This paper aims at demonstrating an accurate and fast power estimation technique. Design/methodology/approach The methodology adopted in the paper is to use input patterns with the predefined statistical characteristics which helps to analyze the average power consumption of the different intellectual-property (IP) cores and the interconnects/buses in SoC design. Similarly the paper has implemented Genetic algorithm (GA) to generate sequences of input signals during the power estimation procedure. Findings The GA concurrently optimizes the input signal characteristics that influence the final solution of the pattern. In addition to that, a Monte-Carlo zero-delay simulation is also performed for individual IP core and bus at high-level. By the simple addition of these cores/buses, power is predicted by a novel macro-model function. In experiments, the average error is estimated at 13.84%. Research limitations/implications To present the research findings with clarity and to avoid complexities, the paper does not consider delay factors like glitches, jitter etc. in the power model. Practical implications The proposed methodology allowed accurate power/energy analysis of practical applications mapped onto Network-on-Chip (NoC) based Multiprocessors SoC platform. It enables the performance analysis of different design alternatives under the load imposed by complex applications. Originality/value This paper is an original contribution and the results demonstrate that our novel technique could be implemented to achieve fast and accurate power estimation in the early stage of any SoC design.

Sign in / Sign up

Export Citation Format

Share Document