scholarly journals FPGA-Based Doppler Frequency Estimator for Real-Time Velocimetry

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 456 ◽  
Author(s):  
Stefano Ricci ◽  
Valentino Meacci
Keyword(s):  
Real Time ◽  
Doppler Shift ◽  
Doppler Frequency ◽  
Low Noise ◽  
Doppler Spectrum ◽  
Frequency Interval ◽  
Field Programmable ◽  
Real Time Applications ◽  
And Performance ◽  
Frequency Estimator

In range-Doppler ultrasound applications, the velocity of a target can be measured by transmitting a mechanical wave, and by evaluating the Doppler shift present on the received echo. Unfortunately, detecting the Doppler shift from the received Doppler spectrum is not a trivial task, and several complex estimators, with different features and performance, have been proposed in the literature for achieving this goal. In several real-time applications, hundreds of thousands of velocity estimates must be produced per second, and not all of the proposed estimators are capable of performing at these high rates. In these challenging conditions, the most widely used approaches are the full centroid frequency estimate or the simple localization of the position of the spectrum peak. The first is more accurate, but the latter features a very quick and straightforward implementation. In this work, we propose an alternative Doppler frequency estimator that merges the advantages of the aforementioned approaches. It exploits the spectrum peak to get an approximate position of the Doppler frequency. Then, centered in this position, a centroid search is applied on a reduced frequency interval to refine the estimate. Doppler simulations are used to compare the accuracy and precision performance of the proposed algorithm with respect to current state of the art approaches. Finally, a Field Programmable Gate Array (FPGA) implementation is proposed that is capable of producing more than 200 k low noise estimates per second, which is suitable for the most demanding real-time applications.

SS-OCT and FD-OCT System Prototyping Using LabVIEW FPGA

2011 ◽  
Author(s):  
Zach Olson
Keyword(s):  
Real Time ◽  
Graphics Processing Units ◽  
Image Data ◽  
Light Sources ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Labview Fpga ◽  
And Performance ◽  
Control Light ◽  
The Cost

Optical coherence tomography (OCT) techniques have opened up a number of new medical imaging applications in research and clinical applications. Key application areas include cancer research, vascular applications such as imaging arterial plaque, and ophthalmology applications such as pre and post-operative cataract surgery imaging. Emerging Technologies in galvo control, light sources, detector technologies, and parallel hardware-based processing are increasing the quality and performance of images, as well as reducing the cost and footprint of OCT systems. The parallel computing capabilities of field programmable gate arrays (FPGAs), multi-core processors, and graphics processing units (GPUs) have enabled real-time OCT image processing, which provides real-time image data to support surgical procedures.

MISS RATIO IMPROVEMENT FOR REAL-TIME APPLICATIONS USING FRAGMENTATION-AWARE PLACEMENT

2007 ◽  
Vol 16 (06) ◽  
pp. 997-1010
Author(s):  
AHMED A. ELFARAG ◽  
HATEM M. El-BOGHDADI ◽  
SAMIR I. SHAHEEN
Keyword(s):  
Real Time ◽  
Field Programmable Gate Arrays ◽  
Gate Arrays ◽  
Placement Method ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Bottom Left ◽  
Real Time Applications ◽  
Online Placement ◽  
Best Fit

Partially reconfigurable field-programmable gate arrays (FPGAs) allow parts of the chip to be configured at runtime where each part could hold an independent task. Online placement of these tasks result in area fragmentation leading to poor utilization of chip resources. In this paper, we propose a new metric for measuring area fragmentation. The new fragmentation metric gives an indication to the continuity of the occupied (or free) space and not the amount of occupied space. We show how this metric can be extended for multidimensional structures. We also show how this metric can be computed efficiently at runtime. Next, we use this measure during online placement of tasks on FPGAs, such that the chip fragmentation is reduced. Our results show improvement of chip utilization when using this fragmentation aware placement method over other placement methods with well-known bottom left, first fit, and best-fit placement strategies. In real-time environment, we achieve an improvement in miss ratio when using the fragmentation-aware placement over the bottom left placement strategy.

scholarly journals Monitoring and controlling the speed and direction of a DC motor through FPGA and comparison of FPGA for speed and performance optimization

2021 ◽  
Vol 11 (5) ◽  
pp. 3903
Author(s):  
Huda M. Abdul Abbas ◽  
Raad Farhood Chisab ◽  
Mohannad Jabbar Mnati
Keyword(s):  
Real Time ◽  
Performance Optimization ◽  
Pulse Width Modulation ◽  
Electronic Device ◽  
Low Cost ◽  
Dc Motor ◽  
Know How ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
And Performance

<span lang="EN-US">We are living in the 21<sup>st</sup> century, an era of acquiring necessity in one click. As we, all know that technology is continuously reviving to stay ahead of advancements taking place in this world of making things easier for mankind. Technology has been putting his part in introducing different projects as we have used the field programmable gate arrays (FPGAs) development board of low cost and programmable logic done by the new evolvable cyclone software is optimized for specific energy based on Altera Cyclone II (EP2C5T144) through which we can control the speed of any electronic device or any Motor Control IP product targeted for the fan and pump. Altera Cyclone FPGAs’ is a board through which we can monitor the speed and direction of the DC motor. As we know how to make understand, dynamic analog input using an A-to-D convertor and we know how to create pulse width modulation (PWM) output with FPGA. Therefore, by combining these two functions we can create an FPGA DC motor controller. Our paper is divided into three parts: First, all of us will attempt to imitate the issue and can try to look for its answer. Secondly, we will try to verify the solution for real-time. In addition, in the last step, we will verify the solution on the real-time measurements.</span>

scholarly journals A Homogeneous Algorithm for Motion Estimation and Compensation by Using Cellular Neural Networks

2010 ◽  
Vol 5 (5) ◽  
pp. 719 ◽  
Author(s):  
Cristian Grava ◽  
Alexandru Gacsádi ◽  
Ioan Buciu
Keyword(s):  
Neural Networks ◽  
Motion Estimation ◽  
Real Time ◽  
Cellular Neural Networks ◽  
Image Sequences ◽  
Artificial Vision ◽  
Real Time Image ◽  
Field Programmable ◽  
Real Time Applications ◽  
Time Image

In this paper we present an original implementation of a homogeneous algorithm for motion estimation and compensation in image sequences, by using Cellular Neural Networks (CNN). The CNN has been proven their efficiency in real-time image processing, because they can be implemented on a CNN chip or they can be emulated on Field Programmable Gate Array (FPGA). The motion information is obtained by using a CNN implementation of the well-known Horn &amp; Schunck method. This information is further used in a CNN implementation of a motion-compensation method. Through our algorithm we obtain a homogeneous implementation for real-time applications in artificial vision or medical imaging. The algorithm is illustrated on some classical sequences and the results confirm the validity of our algorithm.

Field Programmable Gate Array (FPGA) Based Microwave Oven

2019 ◽  
Vol 892 ◽  
pp. 120-126
Author(s):  
Thangavel Bhuvaneswari ◽  
Nor Hidayati Abdul Aziz ◽  
Jakir Hossen ◽  
Chinthakunta Venkataseshaiah
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
Controller Design ◽  
Microwave Oven ◽  
High Potential ◽  
Verilog Hdl ◽  
Quartus Ii ◽  
Field Programmable ◽  
Real Time Applications ◽  
Simulation Results

In this paper, an FPGA-based microwave oven controller design which can be implemented using Altera DE1 development board is presented. The motivation for this work is to explore FPGA for real time applications. First, a microwave oven controller design architecture that could fit into Altera DE1 board, utilizing on-board peripherals is developed. Then, using the proposed architecture, the design is implemented using Verilog HDL. The microwave oven functionalities are demonstrated using Altera DE1 development board by means of Quartus II 13.0 software. The testbenches are created and waveforms are generated using Modelsim 10.1d software. The simulation results for various cases have been presented and the results confirmed that all the basic functionalities of a practical microwave oven can be realized. The proposed FPGA based controller has a high potential for incorporation in microwave ovens.

scholarly journals DANAE++: A Smart Approach for Denoising Underwater Attitude Estimation

2021 ◽  
Author(s):  
Paolo Russo ◽  
Fabiana Di Ciaccio ◽  
Salvatore Troisi
Keyword(s):  
Deep Learning ◽  
Kalman Filter ◽  
Real Time ◽  
Denoising Autoencoder ◽  
Orientation Estimation ◽  
Underwater Robots ◽  
Underwater Environment ◽  
Real Time Applications ◽  
And Performance ◽  
Vehicle Positioning

One of the main issues for underwater robots navigation is represented by the accurate vehicle positioning, which heavily depends on the orientation estimation phase. The systems employed to this scope are affected by different noise typologies, mainly related to the sensors and to the irregular noise of the underwater environment. Filtering algorithms can reduce their effect if opportunely configured, but this process usually requires fine techniques and time. This paper presents DANAE++, an improved denoising autoencoder based on DANAE, which is able to recover Kalman Filter IMU/AHRS orientation estimations from any kind of noise, independently of its nature. This deep learning-based architecture already proved to be robust and reliable, but in its enhanced implementation significant improvements are obtained both in terms of results and performance. In fact, DANAE++is able to denoise the three angles describing the attitude at the same time, and that is verified also on the estimations provided by the more performing Extended KF. Further tests could make this method suitable for real-time applications on navigation tasks.

An Architecture-Based Adaptation Framework for Soft Real-Time Applications

2010 ◽  
Vol 1 (4) ◽  
pp. 12-25
Author(s):  
Ning Gui ◽  
Hong Sun ◽  
Chris Blondia
Keyword(s):  
Real Time ◽  
Unified Framework ◽  
Time Component ◽  
The Face ◽  
Real Time Applications ◽  
And Performance ◽  
Time Changes ◽  
Control Application ◽  
Time Systems ◽  
Real Time Application

Real-time systems are increasingly used in dynamic changing environments with variable user needs hosting real-time applications ranging in number and nature over time. However, to the authors’ knowledge, no unified framework exists that is able to cope with those competing real-time concerns across multiple real-time application domains. This paper proposes an architecture-based framework for managing real-time components’ dependence and lifecycle in an effective and uniform way. A real-time component runtime service is proposed here to maintain the global view, control the whole lifecycle of the components, and keep existing real-time components’ promised contracts in the face of run-time changes. This framework is designed to be easily extended with other constraint resolving policies as well as dependence descriptions languages. At end of this paper, the framework is tested by a simulated control application via adaptation and performance aspects.

scholarly journals A Digital Beamformer for the PHAROS2 Phased Array Feed

2020 ◽  
Vol 09 (03) ◽  
pp. 2050013
Author(s):  
A. Melis ◽  
R. Chiello ◽  
G. Comoretto ◽  
R. Concu ◽  
A. Magro ◽  
...  
Keyword(s):  
Phased Array ◽  
Low Frequency ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Processing Module ◽  
Primary Focus ◽  
Single Polarization ◽  
And Performance

PHased Arrays for Reflector Observing Systems (PHAROS) is a C-band (4–8[Formula: see text]GHz) Phased Array Feed (PAF) receiver designed to operate from the primary focus of a large single-dish radio astronomy antenna. It consists of an array of 220-element Vivaldi antennas ([Formula: see text] polarization), cryogenically cooled at roughly 20[Formula: see text]K along with low noise amplifiers (LNAs), and of analogue beamformers cryogenically cooled at roughly 80[Formula: see text]K. PHAROS2, the upgrade of PHAROS, is a PAF demonstrator developed in the framework of the Square Kilometer Array Advanced Instrumentation Program (SKA AIP) with the goal of investigating the potential of the PAF technologies at high frequencies in view of their possible application on the SKA dish telescopes. The PHAROS2 design includes new cryogenically cooled LNAs with state-of-the-art performance, a digital beamformer capable of synthesizing four beams from a sub-array of 24 single-polarization antenna elements, and a C-band multi-channel Warm Section receiver capable of analogue filtering and down-converting the signals from the antennas to a suitable frequency range at the input of the digital backend, providing an instantaneous bandwidth of 275[Formula: see text]MHz for each signal. In this paper, we describe the design and performance of the PHAROS2 digital backend/beamformer, based on the Italian Tile Processing Module (ITPM) hardware, which was initially developed for the SKA Low Frequency Aperture Array (LFAA). The backend was adapted to perform the beamforming for our PAF application. We describe the implementation of the beamformer on the Field Programmable Gate Arrays (FPGAs) of the ITPM and how the backend was successfully used to synthesize four independent beams, both in the laboratory (across the entire 275[Formula: see text]MHz instantaneous bandwidth) and during on-field observations at the BEST-2 array (across 16[Formula: see text]MHz instantaneous bandwidth), which is a subset of the Northern Cross Radio Telescope (located in the district of Bologna, Italy). The beamformer design allows re-scaling to a greater number of beams and wider bandwidths.

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