scholarly journals A Digital Beamformer for the PHAROS2 Phased Array Feed

2020 ◽  
Vol 09 (03) ◽  
pp. 2050013
Author(s):  
A. Melis ◽  
R. Chiello ◽  
G. Comoretto ◽  
R. Concu ◽  
A. Magro ◽  
...  
Keyword(s):  
Phased Array ◽  
Low Frequency ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Processing Module ◽  
Primary Focus ◽  
Single Polarization ◽  
And Performance

PHased Arrays for Reflector Observing Systems (PHAROS) is a C-band (4–8[Formula: see text]GHz) Phased Array Feed (PAF) receiver designed to operate from the primary focus of a large single-dish radio astronomy antenna. It consists of an array of 220-element Vivaldi antennas ([Formula: see text] polarization), cryogenically cooled at roughly 20[Formula: see text]K along with low noise amplifiers (LNAs), and of analogue beamformers cryogenically cooled at roughly 80[Formula: see text]K. PHAROS2, the upgrade of PHAROS, is a PAF demonstrator developed in the framework of the Square Kilometer Array Advanced Instrumentation Program (SKA AIP) with the goal of investigating the potential of the PAF technologies at high frequencies in view of their possible application on the SKA dish telescopes. The PHAROS2 design includes new cryogenically cooled LNAs with state-of-the-art performance, a digital beamformer capable of synthesizing four beams from a sub-array of 24 single-polarization antenna elements, and a C-band multi-channel Warm Section receiver capable of analogue filtering and down-converting the signals from the antennas to a suitable frequency range at the input of the digital backend, providing an instantaneous bandwidth of 275[Formula: see text]MHz for each signal. In this paper, we describe the design and performance of the PHAROS2 digital backend/beamformer, based on the Italian Tile Processing Module (ITPM) hardware, which was initially developed for the SKA Low Frequency Aperture Array (LFAA). The backend was adapted to perform the beamforming for our PAF application. We describe the implementation of the beamformer on the Field Programmable Gate Arrays (FPGAs) of the ITPM and how the backend was successfully used to synthesize four independent beams, both in the laboratory (across the entire 275[Formula: see text]MHz instantaneous bandwidth) and during on-field observations at the BEST-2 array (across 16[Formula: see text]MHz instantaneous bandwidth), which is a subset of the Northern Cross Radio Telescope (located in the district of Bologna, Italy). The beamformer design allows re-scaling to a greater number of beams and wider bandwidths.

scholarly journals FPGAs in Client Compute Hardware

2021 ◽  
Author(s):  
Michael Mattioli
Keyword(s):  
Integrated Circuits ◽  
Field Programmable Gate Arrays ◽  
Gate Arrays ◽  
Application Specific Integrated Circuits ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
And Performance ◽  
Application Specific

<div>Field-programmable gate arrays (FPGAs) are remarkably versatile. FPGAs are used in a wide variety of applications and industries where use of application-specific integrated circuits (ASICs) is less economically feasible. Despite the area, cost, and power challenges designers face when integrating FPGAs into devices, they provide significant security and performance benefits. Many of these benefits can be realized in client compute hardware such as laptops, tablets, and smartphones.</div>

scholarly journals Technologies, Design, and Applications of Low-Noise Amplifiers at Millimetre-Wave: State-of-the-Art and Perspectives

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1222 ◽  
Author(s):  
Longhi ◽  
Pace ◽  
Colangeli ◽  
Ciccognani ◽  
Limiti
Keyword(s):  
Integrated Circuit ◽  
Noise Figure ◽  
State Of The Art ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Wave State ◽  
Millimetre Wave ◽  
Monolithic Microwave Integrated Circuit ◽  
V Band ◽  
And Performance

An overview of applicable technologies and design solutions for monolithic microwave integrated circuit (MMIC) low-noise amplifiers (LNAs) operating at millimeter-wave are provided in this paper. The review starts with a brief description of the targeted applications and corresponding systems. Advanced technologies are presented highlighting potentials and drawbacks related to the considered possibilities. Design techniques, applicable to different requirements, are presented and analyzed. An LNA operating at V-band (59–66 GHz) is designed and tested following the presented guidelines, demonstrating state-of-the-art results in terms of noise figure (average NF < 2 dB). A state-of-the-art table, reporting recent results available in open literature on this topic, is provided and examined, focusing on room temperature operation and performance in cryogenic environment. Finally, trends versus frequency and perspectives are outlined.

SS-OCT and FD-OCT System Prototyping Using LabVIEW FPGA

2011 ◽  
Author(s):  
Zach Olson
Keyword(s):  
Real Time ◽  
Graphics Processing Units ◽  
Image Data ◽  
Light Sources ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Labview Fpga ◽  
And Performance ◽  
Control Light ◽  
The Cost

Optical coherence tomography (OCT) techniques have opened up a number of new medical imaging applications in research and clinical applications. Key application areas include cancer research, vascular applications such as imaging arterial plaque, and ophthalmology applications such as pre and post-operative cataract surgery imaging. Emerging Technologies in galvo control, light sources, detector technologies, and parallel hardware-based processing are increasing the quality and performance of images, as well as reducing the cost and footprint of OCT systems. The parallel computing capabilities of field programmable gate arrays (FPGAs), multi-core processors, and graphics processing units (GPUs) have enabled real-time OCT image processing, which provides real-time image data to support surgical procedures.

scholarly journals The 1.3mm Full-Stokes Polarization System at CARMA

2015 ◽  
Vol 04 (01n02) ◽  
pp. 1550005 ◽  
Author(s):  
Charles L. H. Hull ◽  
Richard L. Plambeck
Keyword(s):  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Position Angle ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Beam Polarization ◽  
Circular Polarizer ◽  
Angle Measurements ◽  
Millimeter Wavelengths ◽  
And Performance

The CARMA 1.3[Formula: see text]mm polarization system consists of dual-polarization receivers that are sensitive to right- (R) and left-circular (L) polarization, and a spectral-line correlator that measures all four cross polarizations ([Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text]) on each of the 105 baselines connecting the 15 telescopes. Each receiver comprises a single feed horn, a waveguide circular polarizer, an orthomode transducer (OMT), two heterodyne mixers, and two low-noise amplifiers (LNAs), all mounted in a cryogenically cooled dewar. Here we review the basics of polarization observations, describe the construction and performance of key receiver components (circular polarizer, OMT, and mixers — but not the correlator), and discuss in detail the calibration of the system, particularly the calibration of the R–L phase offsets and the polarization leakage corrections. The absolute accuracy of polarization position angle measurements was checked by mapping the radial polarization pattern across the disk of Mars. Transferring the Mars calibration to the well-known polarization calibrator 3C286, we find a polarization position angle of [Formula: see text] for 3C286 at 225[Formula: see text]GHz, consistent with other observations at millimeter wavelengths. Finally, we consider what limitations in accuracy are expected due to the signal-to-noise ratio, dynamic range, and primary beam polarization.

scholarly journals Sparse Cholesky Factorization on FPGA Using Parameterized Model

2017 ◽  
Vol 2017 ◽  
pp. 1-11
Author(s):  
Yichun Sun ◽  
Hengzhu Liu ◽  
Tong Zhou
Keyword(s):  
Integrated Circuit ◽  
Sparse Matrix ◽  
Fundamental Problem ◽  
Performance Model ◽  
Cholesky Factorization ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Application Specific Integrated Circuit ◽  
Parameterized Model ◽  
And Performance

Cholesky factorization is a fundamental problem in most engineering and science computation applications. When dealing with a large sparse matrix, numerical decomposition consumes the most time. We present a vector architecture to parallelize numerical decomposition of Cholesky factorization. We construct an integrated analytical parameterized performance model to accurately predict the execution times of typical matrices under varying parameters. Our proposed approach is general for accelerator and limited by neither field-programmable gate arrays (FPGAs) nor application-specific integrated circuit. We implement a simplified module in FPGAs to prove the accuracy of the model. The experiments show that, for most cases, the performance differences between the predicted and measured execution are less than 10%. Based on the performance model, we optimize parameters and obtain a balance of resources and performance after analyzing the performance of varied parameter settings. Comparing with the state-of-the-art implementation in CPU and GPU, we find that the performance of the optimal parameters is 2x that of CPU. Our model offers several advantages, particularly in power consumption. It provides guidance for the design of future acceleration components.

scholarly journals Monitoring and controlling the speed and direction of a DC motor through FPGA and comparison of FPGA for speed and performance optimization

2021 ◽  
Vol 11 (5) ◽  
pp. 3903
Author(s):  
Huda M. Abdul Abbas ◽  
Raad Farhood Chisab ◽  
Mohannad Jabbar Mnati
Keyword(s):  
Real Time ◽  
Performance Optimization ◽  
Pulse Width Modulation ◽  
Electronic Device ◽  
Low Cost ◽  
Dc Motor ◽  
Know How ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
And Performance

<span lang="EN-US">We are living in the 21<sup>st</sup> century, an era of acquiring necessity in one click. As we, all know that technology is continuously reviving to stay ahead of advancements taking place in this world of making things easier for mankind. Technology has been putting his part in introducing different projects as we have used the field programmable gate arrays (FPGAs) development board of low cost and programmable logic done by the new evolvable cyclone software is optimized for specific energy based on Altera Cyclone II (EP2C5T144) through which we can control the speed of any electronic device or any Motor Control IP product targeted for the fan and pump. Altera Cyclone FPGAs’ is a board through which we can monitor the speed and direction of the DC motor. As we know how to make understand, dynamic analog input using an A-to-D convertor and we know how to create pulse width modulation (PWM) output with FPGA. Therefore, by combining these two functions we can create an FPGA DC motor controller. Our paper is divided into three parts: First, all of us will attempt to imitate the issue and can try to look for its answer. Secondly, we will try to verify the solution for real-time. In addition, in the last step, we will verify the solution on the real-time measurements.</span>

EXTENDABLE AND DYNAMICALLY RECONFIGURABLE MULTI-PROTOCOL FIREWALL

2005 ◽  
Vol 15 (02) ◽  
pp. 363-371 ◽  
Author(s):  
SUNG LY ◽  
ABBAS BIGDELI
Keyword(s):  
Low Cost ◽  
Local Network ◽  
Gigabit Ethernet ◽  
Dynamically Reconfigurable ◽  
High Data ◽  
Security Issues ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
And Performance ◽  
Networking Technology

Security issues within a networking environment are critical, as attacks or intrusions can come from many different sources. Firewalls are an effective tool used for intrusion detection and provide protection against attacks on a system or network. In the past, protection barriers for a local network have been provided using software solutions. Emerging multi-gigabit networking technology and the high uptake of gigabit Ethernet has rendered these solutions inefficient as it cannot cope with the high data rate. In this paper, a new approach using reconfigurable hardware such as Field Programmable Gate Arrays is proposed to provide the flexibility and performance required for a gigabit firewall. The solution is extendable, has low cost and is capable of scanning multiple protocols. The design approach will allow it to be easily ported over to another family of chips with no or minor modification.

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