Sensitive, Linear, Robust Current-To-Time Converter Circuit for Vehicle Automation Application

Voltage-to-time and current-to-time converters have been used in many recent works as a voltage-to-digital converter for artificial intelligence applications. In general, most of the previous designs use the current-starved technique or a capacitor-based delay unit, which is non-linear, expensive, and requires a large area. In this paper, we propose a highly linear current-to-digital converter. An optimization method is also proposed to generate the optimal converter design containing the smallest number of PMOS and sensitive circuits such as a differential amplifier. This enabled our design to be more stable and robust toward negative bias temperature instability (NBTI) and process variation. The proposed converter circuit implements the point-wise conversion from current-to-time, and it can be used directly for a variety of applications, such as analog-to-digital converters (ADC), used in built-in computational random access (C-RAM) memory. The conversion gain of the proposed circuit is 3.86 ms/A, which is 52 times greater than the conversion gains of state-of-the-art designs. Further, various time-to-digital converter (TDC) circuits are reviewed for the proposed current-to-time converter, and we recommend one circuit for a complete ADC design.

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Reducing Design Margins by Adaptive Compensation for Thermal and Aging Variations

Sustainable ICTs and Management Systems for Green Computing ◽

10.4018/978-1-4666-1839-8.ch009 ◽

2012 ◽

pp. 201-230

Author(s):

Zhenyu Qi ◽

Yan Zhang ◽

Mircea Stan

Keyword(s):

Design Parameters ◽

Worst Case Analysis ◽

Transimpedance Amplifier ◽

Large Area ◽

Negative Bias Temperature Instability ◽

Worst Case ◽

Adaptive Computation ◽

Bias Temperature Instability ◽

Computation Efficiency ◽

On Chip

Corner-based design and verification are based on worst-case analysis, thus introducing over-pessimism and large area and power overhead and leading to unnecessary energy consumption. Typical case-based design and verification maximize energy efficiency through design margins reduction and adaptive computation, thus helping achieve sustainable computing. Dynamically adapting to manufacturing, environmental, and usage variations is the key to shaving unnecessary design margins, which requires on-chip modules that can sense and configure design parameters both globally and locally to maximize computation efficiency, and maintain this efficiency over the lifetime of the system. This chapter presents an adaptive threshold compensation scheme using a transimpedance amplifier and adaptive body biasing to overcome the effects of temperature variation, reliability degradation, and process variation. The effectiveness and versatility of the scheme are demonstrated with two example applications, one as a temperature aware design to maintain IONto IOFFcurrent ratio, the other as a reliability sensor for NBTI (Negative Bias Temperature Instability).

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Oversampling Analog-to-Digital Converter Design

21st International Conference on VLSI Design (VLSID 2008) ◽

10.1109/vlsi.2008.130 ◽

2008 ◽

Cited By ~ 1

Author(s):

Shanthi Pavan ◽

Nagendra Krishnapura

Keyword(s):

Analog To Digital Converter ◽

Digital Converter ◽

Analog To Digital ◽

Converter Design

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Countermeasures against NBTI degradation on 6T-SRAM cells

Advances in Radio Science ◽

10.5194/ars-9-255-2011 ◽

2011 ◽

Vol 9 ◽

pp. 255-261 ◽

Cited By ~ 8

Author(s):

E. Glocker ◽

D. Schmitt-Landsiedel ◽

S. Drapatz

Keyword(s):

Random Access ◽

Memory Cell ◽

Random Access Memory ◽

Aging Effect ◽

Static Random Access Memory ◽

Negative Bias Temperature Instability ◽

Access Memory ◽

Bias Temperature Instability ◽

Simulation Results ◽

Degradation Effect

Abstract. In current process technologies, NBTI (negative bias temperature instability) has the most severe aging effect on static random access memory (SRAM) cells. This degradation effect causes loss of stability. In this paper countermeasures against this hazard are presented and quantified via simulations in 90 nm process technologies by the established metrics SNMread, SNMhold, Iread and Write Level. With regard to simulation results and practicability best candidates are chosen and, dependent on individual preferences at memory cell design, the best countermeasure in each case is recommended.

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