scholarly journals Two-Stage Checkpoint Based Security Monitoring and Fault Recovery Architecture for Embedded Processor

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1165
Author(s):  
Xiang Wang ◽  
Zongmin Zhao ◽  
Dongdong Xu ◽  
Zhun Zhang ◽  
Qiang Hao ◽  
...  
Keyword(s):  
Embedded System ◽  
Basic Block ◽  
Program Execution ◽  
Fault Recovery ◽  
Transient Faults ◽  
Two Stage ◽  
Embedded Processor ◽  
Research Attention ◽  
Security Monitoring ◽  
Integrity Check

Nowadays, the secure program execution of embedded processor has attracted considerable research attention, since more and more code tampering attacks and transient faults are seriously affecting the security of embedded processors. The program monitoring and fault recovery strategies are not only closely related to the security of embedded devices, but also directly affect the performance of the processor. This paper presents a security monitoring and fault recovery architecture for run-time program execution, which takes regular backup copies of the two-stage checkpoint. In this framework, the integrity check technology based on the basic block (BB) is utilized to monitor the program execution in real-time, while the rollback operation is taken once the integrity check is failed. In addition, a Monitoring Cache (M-Cache) is built to buffer the reference data for integrity checking. Moreover, a recovery strategy mainly for three tampered positions (registers in processor, instructions in Cache, and codes in memory) is provided to ensure the smooth running of the embedded system. Finally, the open RISC processor is adopted to implement and verify the presented security architecture, which has been proved to be effective for program detection in the execution of tamper attack and quick recovery of the running environment as well as code.

scholarly journals Hardware-Assisted Security Monitoring Unit for Real-Time Ensuring Secure Instruction Execution and Data Processing in Embedded Systems

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1450
Author(s):  
Xiang Wang ◽  
Zhun Zhang ◽  
Qiang Hao ◽  
Dongdong Xu ◽  
Jiqing Wang ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Data Processing ◽  
Embedded System ◽  
High Performance ◽  
Program Execution ◽  
Security Monitoring ◽  
Railway Systems ◽  
On Chip ◽  
Capability Evaluation ◽  
Security Capability

The hardware security of embedded systems is raising more and more concerns in numerous safety-critical applications, such as in the automotive, aerospace, avionic, and railway systems. Embedded systems are gaining popularity in these safety-sensitive sectors with high performance, low power, and great reliability, which are ideal control platforms for executing instruction operation and data processing. However, modern embedded systems are still exposing many potential hardware vulnerabilities to malicious attacks, including software-level and hardware-level attacks; these can cause program execution failure and confidential data leakage. For this reason, this paper presents a novel embedded system by integrating a hardware-assisted security monitoring unit (SMU), for achieving a reinforced system-on-chip (SoC) on ensuring program execution and data processing security. This architecture design was implemented and evaluated on a Xilinx Virtex-5 FPGA development board. Based on the evaluation of the SMU hardware implementation in terms of performance overhead, security capability, and resource consumption, the experimental results indicate that the SMU does not lead to a significant speed degradation to processor while executing different benchmarks, and its average performance overhead reduces to 2.18% on typical 8-KB I/D-Caches. Security capability evaluation confirms the monitoring effectiveness of SMU against both instruction and data tampering attacks. Meanwhile, the SoC satisfies a good balance between high-security and resource overhead.

An M-Cache-Based Security Monitoring and Fault Recovery Architecture for Embedded Processor

2020 ◽  
Vol 28 (11) ◽  
pp. 2314-2327
Author(s):  
Xiang Wang ◽  
Zongmin Zhao ◽  
Dongdong Xu ◽  
Zhun Zhang ◽  
Qiang Hao ◽  
...  
Keyword(s):  
Fault Recovery ◽  
Embedded Processor ◽  
Security Monitoring

scholarly journals The Design of a 2D Graphics Accelerator for Embedded Systems

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 469
Author(s):  
Hyun Woo Oh ◽  
Ji Kwang Kim ◽  
Gwan Beom Hwang ◽  
Seung Eun Lee
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Real Time ◽  
Line Drawing ◽  
Cmos Process ◽  
Embedded Processor ◽  
Processor Core ◽  
Field Programmable ◽  
The Embedded System ◽  
Graphics Processing

Recently, advances in technology have enabled embedded systems to be adopted for a variety of applications. Some of these applications require real-time 2D graphics processing running on limited design specifications such as low power consumption and a small area. In order to satisfy such conditions, including a specific 2D graphics accelerator in the embedded system is an effective method. This method reduces the workload of the processor in the embedded system by exploiting the accelerator. The accelerator assists the system to perform 2D graphics processing in real-time. Therefore, a variety of applications that require 2D graphics processing can be implemented with an embedded processor. In this paper, we present a 2D graphics accelerator for tiny embedded systems. The accelerator includes an optimized line-drawing operation based on Bresenham’s algorithm. The optimized operation enables the accelerator to deal with various kinds of 2D graphics processing and to perform the line-drawing instead of the system processor. Moreover, the accelerator also distributes the workload of the processor core by removing the need for the core to access the frame buffer memory. We measure the performance of the accelerator by implementing the processor, including the accelerator, on a field-programmable gate array (FPGA), and ascertaining the possibility of realization by synthesizing using the 180 nm CMOS process.

scholarly journals Controlling Embedded Systems Remotely via Internet-of-Things Based on Emotional Recognition

2020 ◽  
Vol 2020 ◽  
pp. 1-10
Author(s):  
Mohammad J. M. Zedan ◽  
Ali I. Abduljabbar ◽  
Fahad Layth Malallah ◽  
Mustafa Ghanem Saeed
Keyword(s):  
Machine Learning ◽  
Feature Extraction ◽  
Remote Control ◽  
Embedded Systems ◽  
Embedded System ◽  
Electronic Devices ◽  
Recognition Rate ◽  
Disabled People ◽  
Research Attention ◽  
Image Preprocessing

Nowadays, much research attention is focused on human–computer interaction (HCI), specifically in terms of biosignal, which has been recently used for the remote controlling to offer benefits especially for disabled people or protecting against contagions, such as coronavirus. In this paper, a biosignal type, namely, facial emotional signal, is proposed to control electronic devices remotely via emotional vision recognition. The objective is converting only two facial emotions: a smiling or nonsmiling vision signal captured by the camera into a remote control signal. The methodology is achieved by combining machine learning (for smiling recognition) and embedded systems (for remote control IoT) fields. In terms of the smiling recognition, GENKl-4K database is exploited to train a model, which is built in the following sequenced steps: real-time video, snapshot image, preprocessing, face detection, feature extraction using HOG, and then finally SVM for the classification. The achieved recognition rate is up to 89% for the training and testing with 10-fold validation of SVM. In terms of IoT, the Arduino and MCU (Tx and Rx) nodes are exploited for transferring the resulting biosignal remotely as a server and client via the HTTP protocol. Promising experimental results are achieved by conducting experiments on 40 individuals who participated in controlling their emotional biosignals on several devices such as closing and opening a door and also turning the alarm on or off through Wi-Fi. The system implementing this research is developed in Matlab. It connects a webcam to Arduino and a MCU node as an embedded system.

scholarly journals Implementation of master-slave method on multiprocessor-based embedded system: case study on mobile robot

2018 ◽  
Vol 7 (2.2) ◽  
pp. 53
Author(s):  
Agusma Wajiansyah ◽  
Hari Purwadi ◽  
Asrina Astagani ◽  
Supriadi Supriadi
Keyword(s):  
Embedded Systems ◽  
Mobile Robot ◽  
Embedded System ◽  
Execution Time ◽  
Experimental Results ◽  
Program Execution ◽  
Time Average ◽  
Single Processor ◽  
Number Of Iterations

In this research the master-slave method implemented on an embedded system using 3 processor applied to the mobile robot, to know the speed of program execution of robot. As a comparison is also used a robot with an embedded system based on single processor. From the experimental results, by applying the slave master method obtained the execution time of 546,5 μs and the number of iteration 1079, while for single processor-based system obtained execution time average 67828 μs and the amount of iteration average 147 times. Where the number of iterations is obtained by running the robot for 10 s. From this experiment, it can be concluded that there is a performance increase of 7.3% when compared to embedded systems based on single processor. 

Realization of Algorithm for Wideband Sound Source Localization in Video Monitoring System

2013 ◽  
Vol 416-417 ◽  
pp. 1086-1091
Author(s):  
Lei Li ◽  
Yong Gang Su ◽  
Shen Tian ◽  
Yong Li ◽  
Zhi Tong Li
Keyword(s):  
Embedded System ◽  
Sound Source ◽  
Social Research ◽  
Microphone Array ◽  
Blind Spot ◽  
Video Tracking ◽  
Time Delay Estimation ◽  
Video Monitoring ◽  
Localization Algorithm ◽  
Security Monitoring

Video security monitoring has become the focus of social research and development; however, since the camera cannot automatically rotate, there is a blind spot in traditional security monitoring. Considering the abnormal often happens accompanied by corresponding sounds (e.g., where there is an explosion , there will be the sound of explosions), therefore, for compensating the blind spot , the auditory function can be added to the camera to track the direction of sound source automatically which requires the two-dimensional (2-D) localization of sound source to complete , at the mean time , the localization algorithm should be capable of tracking all of the source signals ,as well as be real-time to make the video tracking to be achieved by turning the camera toward sound source timely. This paper realizes the localization of wideband speech signal in video monitoring by using modern signal processing method, linear microphone array, positioning thought based on time delay estimation, frequency domain transform, and spectrum-search method based on energy value. Both the early simulation and late DSP-based embedded system platform have verified the feasibility of the method.

Efficient Security Monitoring with the Core Debug Interface in an Embedded Processor

2016 ◽  
Vol 22 (1) ◽  
pp. 1-29 ◽  
Author(s):  
Jinyong Lee ◽  
Ingoo Heo ◽  
Yongje Lee ◽  
Yunheung Paek
Keyword(s):  
Embedded Processor ◽  
Security Monitoring ◽  
The Core

scholarly journals Fog-Computing-Based Heartbeat Detection and Arrhythmia Classification Using Machine Learning

Algorithms ◽  
2019 ◽  
Vol 12 (2) ◽  
pp. 32 ◽  
Author(s):  
Alessandro Scirè ◽  
Fabrizio Tropeano ◽  
Aris Anagnostopoulos ◽  
Ioannis Chatzigiannakis
Keyword(s):  
Machine Learning ◽  
Embedded System ◽  
Fog Computing ◽  
Cloud Services ◽  
Sensor Data ◽  
High Detection Rate ◽  
Embedded Processor ◽  
Machine Learning Applications ◽  
Active Research ◽  
Asymmetric Multicore

Designing advanced health monitoring systems is still an active research topic. Wearable and remote monitoring devices enable monitoring of physiological and clinical parameters (heart rate, respiration rate, temperature, etc.) and analysis using cloud-centric machine-learning applications and decision-support systems to predict critical clinical states. This paper moves from a totally cloud-centric concept to a more distributed one, by transferring sensor data processing and analysis tasks to the edges of the network. The resulting solution enables the analysis and interpretation of sensor-data traces within the wearable device to provide actionable alerts without any dependence on cloud services. In this paper, we use a supervised-learning approach to detect heartbeats and classify arrhythmias. The system uses a window-based feature definition that is suitable for execution within an asymmetric multicore embedded processor that provides a dedicated core for hardware assisted pattern matching. We evaluate the performance of the system in comparison with various existing approaches, in terms of achieved accuracy in the detection of abnormal events. The results show that the proposed embedded system achieves a high detection rate that in some cases matches the accuracy of the state-of-the-art algorithms executed in standard processors.

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