scholarly journals Design and VLSI Implementation of a Reduced-Complexity Sorted QR Decomposition for High-Speed MIMO Systems

Electronics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 1657
Author(s):  
Lu Sun ◽  
Bin Wu ◽  
Tianchun Ye

In this article, a low-complexity and high-throughput sorted QR decomposition (SQRD) for multiple-input multiple-output (MIMO) detectors is presented. To reduce the heavy hardware overhead of SQRD, we propose an efficient SQRD algorithm based on a novel modified real-value decomposition (RVD). Compared to the latest study, the proposed SQRD algorithm can save the computational complexity by more than 44.7% with similar bit error rate (BER) performance. Furthermore, a corresponding deeply pipelined hardware architecture implemented with the coordinate rotation digital computer (CORDIC)-based Givens rotation (GR) is designed. In the design, we propose a time-sharing Givens rotation structure utilizing CORDIC modules in idle state to share the concurrent GR operations of other CORDIC modules, which can further reduce hardware complexity and improve hardware efficiency. The proposed SQRD processor is implemented in SMIC 55-nm CMOS technology, which processes 62.5 M SQRD per second at a 250-MHz operating frequency with only 176.5 kilo-gates. Compared to related studies, the proposed design has the best normalized hardware efficiency and achieves a 6-Gbps MIMO data rate which can support current high-speed wireless communication systems such as IEEE 802.11ax.

2021 ◽  
Vol 2 (2) ◽  
pp. 109-127
Author(s):  
George C. Alexandropoulos

The hardware complexity of the analog Self-Interference (SI) canceler in conventional full duplex Multiple Input Multiple Output (MIMO) designs mostly scales with the number of transmit and receive antennas, thus exploiting the benefits of analog cancellation becomes impractical for full duplex MIMO transceivers, even for a moderate number of antennas. In this paper, we provide an overview of two recent hardware architectures for the analog canceler comprising of reduced number of cancellation elements, compared to the state of the art, and simple multiplexers for efficient signal routing among the transceiver radio-frequency chains. The one architecture is based on analog taps and the other on AUXiliary (AUX) Transmitters (TXs). In contrast to the available analog cancellation architectures, the values for each tap or each AUX TX and the configuration of the multiplexers are jointly designed with the digital transceiver beamforming filters according to desired performance objectives. We present a general optimization framework for the joint design of analog SI cancellation and digital beamforming, and detail an example algorithmic solution for the sum-rate optimization objective. Our representative computer simulation results demonstrate the superiority, both in terms of hardware complexity and achievable performance, of the presented low complexity full duplex MIMO schemes over the relative available ones in the literature. We conclude the paper with a discussion on recent simultaneous transmit and receive operations capitalizing on the presented architectures, and provide a list of open challenges and research directions for future FD MIMO communication systems, as well as their promising applications.


Author(s):  
Hoai Trung Tran

The Multiple Input Multiple Output (MIMO) systems using relays are of interest for high-speed radio communication systems. Currently, most of the articles are interested in the model of three nodes with purposes such as increasing the channel capacities (mutual information) or reducing the minimum mean square of error. This paper extends to more than one relay and is concerned with the maximum channel capacity. It is assumed that the channel matrices between source and relay as well as relay and receiver are random matrices; the relay precoders are also assumed to be random and known at the receiver. The article proposes that the Lagrange multiplier finding algorithm using the Newton – Raphson optimization method is more straightforward than the traditional finding algorithm using the first and second derivatives but still gives a higher channel capacity.


2018 ◽  
Vol 27 (14) ◽  
pp. 1850220 ◽  
Author(s):  
Wei-Yang Chen ◽  
Chung-An Shen

This paper presents the VLSI architecture of a low-latency and high-throughput sorted-QR decomposition (SQRD) engine for multiple-input multiple-output (MIMO) communication systems. In order to achieve a high processing throughput, the proposed design is architected based on a novel pipelined Givens rotation (GR) structure comprising of multi-dimension COordinate rotation DIgital computer (CORDIC) (MD-CORDIC) processing elements (PEs). Moreover, this design delivers the vector norm and conducts the sorting operation as a by-product of the vectoring operation on the execution flow of the CORDIC process. Therefore, excessive overheads for norm-calculation and sorting are excluded, and thus the latency is greatly reduced and throughput is enhanced. In addition, the proposed SQRD engine is operating directly on the complex-valued channel matrix to avoid the matrix augmentation caused by the real-valued decomposition of the channel matrix. This design has been synthesized, placed and routed, and the post-layout estimation results have shown that the processing throughput of the proposed SQRD architecture achieves an approximately 2[Formula: see text] improvement compared to the prior arts.


Author(s):  
Arvind Kakria ◽  
Trilok Chand Aseri

Background & Objective: Wireless communication has immensely grown during the past few decades due to significant demand for mobile access. Although cost-effective as compared to their wired counterpart, maintaining good quality-of-service (QoS) in these networks has always remained a challenge. Multiple-input Multiple-output (MIMO) systems, which consists of multiple transmitter and receiver antennas, have been widely acknowledged for their QoS and transmit diversity. Though suited for cellular base stations, MIMO systems are not suited for small-sized wireless nodes due to their hardware complexity, cost, and increased power requirements. Cooperative communication that allows relays, i.e. mobile or fixed nodes in a communication network, to share their resources and forward other node’s data to the destination node has substituted the MIMO systems nowadays. To harness the full benefit of cooperative communication, appropriate relay node selection is very important. This paper presents an efficient single-hop distributed relay supporting medium access control (MAC) protocol (EDSRS) that works in the single-hop environment and improves the energy efficiency and the life of relay nodes without compensating the throughput of the network. Methods: The protocol has been simulated using NS2 simulator. The proposed protocol is compared with energy efficient cooperative MAC protocol (EECOMAC) and legacy distributed coordination function (DCF) on the basis of throughput, energy efficiency, transmission delay and an end to end delay with various payload sizes. Result and Conclusion: The result of the comparison indicates that the proposed protocol (EDSRS) outperforms the other two protocols.


Author(s):  
В.Б. КРЕЙНДЕЛИН ◽  
М.В. ГОЛУБЕВ

Совместный с прекодингом автовыбор антенн на приемной и передающей стороне - одно из перспективных направлений исследований для реализации технологий Multiple Transmission and Reception Points (Multi-TRP, множество точек передачи и приема) в системах со многими передающими и приемными антеннами Massive MIMO (Multiple-Input-Multiple-Output), которые активно развиваются в стандарте 5G. Проанализированы законодательные ограничения, влияющие на применимость технологий Massive MIMO, и специфика реализации разрабатываемого алгоритма в миллиметровомдиапа -зоне длин волн. Рассмотрены алгоритмы формирования матриц автовыбора антенн как на передающей, так и на приемной стороне. Сформулирована строгая математическая постановка задачи для двух критериев работы алгоритма: максимизация взаимной информации и минимизация среднеквадратичной ошибки. Joint precoding and antenna selection both on transmitter and receiver sides is one of the promising research areas for evolving toward the Multiple Transmission and Reception Points (Multi-TRP) concept in Massive MIMO systems. This technology is under active development in the coming 5G 3GPP releases. We analyze legal restrictions for the implementation of 5G Massive MIMO technologies in Russia and the specifics of the implementation of the developed algorithm in the millimeter wavelength range. Algorithms of antenna auto-selection matrices formation on both transmitting and receiving sides are considered. Two criteria are used for joint antenna selection and precoding: maximizing mutual information and minimizing mean square error.


Author(s):  
Mohammed Qasim Sulttan

<p>Multiple-Input Multiple-Output (MIMO) technique is a key technology to strengthen and achieve high-speed and high-throughput wireless communications. . In recent years, it was observed that frequent detecting techniques could improve the performance (e.g., symbol error rate ‘SER’) of different modern digital communication systems. But these systems faced a problem of high complexity for the practical implementation.  To solve the problem of high complexity, this work proposed Frequent Improve K-best Sphere Decoding (FIKSD) algorithm with stopping rule depending on the Manhattan metric. Manhattan metric is proposed to use with FIKSD in order to achieve the lowest complexity. FIKSD is a powerful tool to achieve a high performance close to the maximum likelihood (ML), with less complexity. The simulation results show a good reduction in computation complexity with a cost of slight performance degradation within 1dB; the proposed FIKSD requires 0% to 94% and 82% to 97% less complexity than Improved K-best Sphere Decoder (IKSD) and K-best Sphere Decoder (KSD) respectively. This makes the algorithm more suitable for implementation in wireless communication systems.</p>


Information ◽  
2019 ◽  
Vol 10 (5) ◽  
pp. 165 ◽  
Author(s):  
Xiaoqing Zhao ◽  
Zhengquan Li ◽  
Song Xing ◽  
Yang Liu ◽  
Qiong Wu ◽  
...  

Massive multiple-input-multiple-output (MIMO) is one of the key technologies in the fifth generation (5G) cellular communication systems. For uplink massive MIMO systems, the typical linear detection such as minimum mean square error (MMSE) presents a near-optimal performance. Due to the required direct matrix inverse, however, the MMSE detection algorithm becomes computationally very expensive, especially when the number of users is large. For achieving the high detection accuracy as well as reducing the computational complexity in massive MIMO systems, we propose an improved Jacobi iterative algorithm by accelerating the convergence rate in the signal detection process.Specifically, the steepest descent (SD) method is utilized to achieve an efficient searching direction. Then, the whole-correction method is applied to update the iterative process. As the result, the fast convergence and the low computationally complexity of the proposed Jacobi-based algorithm are obtained and proved. Simulation results also demonstrate that the proposed algorithm performs better than the conventional algorithms in terms of the bit error rate (BER) and achieves a near-optimal detection accuracy as the typical MMSE detector, but utilizing a small number of iterations.


2013 ◽  
Vol 347-350 ◽  
pp. 3478-3481
Author(s):  
Li Liu ◽  
Jin Kuan Wang ◽  
Xin Song ◽  
Yin Hua Han ◽  
Yu Huan Wang

Maximum likelihood (ML) detection algorithm for multiple input multiple output (MIMO) systems provided the best bit error rate (BER) performance with heavy calculating complexity. The use of QR decomposition with M-algorithm (QRD-M) had been proposed to provide near-ML detection performance and lower calculating complexity. However, its complexity still grew exponentially with increasing dimension of the transmitted signal. To reduce the problem, an improved detection scheme was proposed here. After constructing the tree detecting model of MIMO systems, the ML search of one layer was done, the branch metrics were calculated and sorted, which gave an ordered set of the layer, then depth-first search were used to search the left layers with termination methods. The proposed algorithm provides near QRD-M detection performance.


VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-7
Author(s):  
Zhen-dong Zhang ◽  
Bin Wu ◽  
Yu-mei Zhou ◽  
Xin Zhang

A high-speed low-complexity hardware interleaver/deinterleaver is presented. It supports all 77 802.11n high-throughput (HT) modulation and coding schemes (MCSs) with short and long guard intervals and the 8 non-HT MCSs defined in 802.11a/g. The paper proposes a design methodology that distributes the three permutations of an interleaver to both write address and read address. The methodology not only reduces the critical path delay but also facilitates the address generation. In addition, the complex mathematical formulas are replaced with optimized hardware structures in which hardware intensive dividers and multipliers are avoided. Using 0.13 um CMOS technology, the cell area of the proposed interleaver/deinterleaver is 0.07 mm2, and the synthesized maximal working frequency is 400 MHz. Comparison results show that it outperforms the three other similar works with respect to hardware complexity and max frequency while maintaining high flexibility.


2014 ◽  
Vol 24 (02) ◽  
pp. 1550026 ◽  
Author(s):  
Chang-Kun Yao ◽  
Yun-Ching Tang ◽  
Hongchin Lin

This study proposes an energy-efficient and area-efficient dual-path low-density parity-check (LDPC) with Reed–Solomon (RS) decoder for communication systems. Hardware complexity is reduced by applying a dual-path 2-bit modified layered min-sum algorithm (2M-LMSA) to a (2550, 2040) quasi-cyclic LDPC (QC-LDPC) code with the column and row weights of 3 and 15, respectively. The simplified check node units (CNUs) reduce memory and routing complexity as well as the energy needed to decode each bit. A throughput of 11 Gb/s is achieved by using 90-nm CMOS technology at a clock frequency of 208 MHz at 0.9 V with average power of 244 mW on a chip area of 3.05 mm2. Decoding performance is further improved by appending the (255, 239) RS decoder after the LDPC decoder. The LDPC plus RS decoder consumes the power of 434 mW on the area of 3.45 mm2.


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