scholarly journals A Multi-Sectional Arc Eliminator for Protection of Low Voltage Electrical Equipment

Energies ◽  
2020 ◽  
Vol 13 (3) ◽  
pp. 605
Author(s):  
Karol Nowak ◽  
Jerzy Janiszewski ◽  
Grzegorz Dombek
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Electrical Equipment ◽  
Power Network ◽  
Current Load ◽  
Performance Effectiveness ◽  
Release Times ◽  
Test Circuit ◽  
Electrical Apparatus ◽  
Arcing Fault

The paper presents a system of two oppositely connected multi-sectional thyristor branches. The system works as a multi-sectional arc eliminator (MSAE), protecting low-voltage electrical apparatus against the effects of an arcing fault. MSAE is designed to serve as a device cooperating with protected and secured electrical equipment. The use of thyristors in the proposed solution allows to obtain a high speed of operation, while multi-sectional thyristor branches significantly increase the permissible current load of the arc eliminator. A test circuit was designed and made to test the performance effectiveness of the multi-sectional thyristor arc eliminator. A number of tests were carried out with variable current values in the arc branch, taking into account the influence of thyristor conduction voltage and different thyristor gate release times. It was found that the multi-section thyristor arc eliminator system effectively protects devices powered from low voltage power network against the effects of interference or arc fault.

scholarly journals Thyristor Arc Eliminator for Protection of Low Voltage Electrical Equipment

Energies ◽  
2019 ◽  
Vol 12 (14) ◽  
pp. 2749 ◽  
Author(s):  
Karol Nowak ◽  
Jerzy Janiszewski ◽  
Grzegorz Dombek
Keyword(s):  
Lower Cost ◽  
Low Voltage ◽  
Short Circuit ◽  
Electrical Equipment ◽  
Power Network ◽  
System Operation ◽  
Test Circuit ◽  
Wide Range ◽  
Short Circuit Currents ◽  
Electrical Apparatus

The paper presents the layout of two opposing thyristors working as an Arc Eliminator (AE). The presented solution makes it possible to protect an electrical apparatus against the effects of an arcing fault. An Arc Eliminator is assumed to be a device cooperating with the protected apparatus. Thyristors were used because of their speed of operation and a relatively lower cost compared to other semiconductors with the same current-carrying capacity. The proposed solution, as one of the few currently available, makes it possible to eliminate the fault arc—both at short-circuit currents and current values to which overcurrent protections do not react. A test circuit was designed and made to study the effectiveness of the thyristor arc eliminator. A series of tests was carried out with variable impedance in the arc branch, including the influence of circuit inductance on arc time. It was found that the thyristor arc eliminator effectively protects devices powered from a low voltage power network against the effects of a fault or arc fault. The correctness of system operation for a wide range of impedance changes in the circuit feeding the arc location was demonstrated.

scholarly journals Asymmetric Ge/SiGe coupled quantum well modulators

Nanophotonics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 1765-1773
Author(s):  
Yi Zhang ◽  
Jianfeng Gao ◽  
Senbiao Qin ◽  
Ming Cheng ◽  
Kang Wang ◽  
...  
Keyword(s):  
Energy Consumption ◽  
Quantum Well ◽  
Quantum Wells ◽  
High Speed ◽  
Low Voltage ◽  
Extinction Ratio ◽  
High Frequency Response ◽  
Modulation Format ◽  
Silicon Photonic ◽  
Coupled Quantum Well

Abstract We design and demonstrate an asymmetric Ge/SiGe coupled quantum well (CQW) waveguide modulator for both intensity and phase modulation with a low bias voltage in silicon photonic integration. The asymmetric CQWs consisting of two quantum wells with different widths are employed as the active region to enhance the electro-optical characteristics of the device by controlling the coupling of the wave functions. The fabricated device can realize 5 dB extinction ratio at 1446 nm and 1.4 × 10−3 electrorefractive index variation at 1530 nm with the associated modulation efficiency V π L π of 0.055 V cm under 1 V reverse bias. The 3 dB bandwidth for high frequency response is 27 GHz under 1 V bias and the energy consumption per bit is less than 100 fJ/bit. The proposed device offers a pathway towards a low voltage, low energy consumption, high speed and compact modulator for silicon photonic integrated devices, as well as opens possibilities for achieving advanced modulation format in a more compact and simple frame.

scholarly journals Reliability-Oriented Design of Inverter-Fed Low-Voltage Electrical Machines: Potential Solutions

Energies ◽  
2021 ◽  
Vol 14 (14) ◽  
pp. 4144
Author(s):  
Yatai Ji ◽  
Paolo Giangrande ◽  
Vincenzo Madonna ◽  
Weiduo Zhao ◽  
Michael Galea
Keyword(s):  
Power Density ◽  
High Speed ◽  
High Performance ◽  
Low Voltage ◽  
Electrical Machines ◽  
Design Stage ◽  
Switching Frequency ◽  
Special Focus ◽  
Electrical Machine ◽  
Engineering Approach

Transportation electrification has kept pushing low-voltage inverter-fed electrical machines to reach a higher power density while guaranteeing appropriate reliability levels. Methods commonly adopted to boost power density (i.e., higher current density, faster switching frequency for high speed, and higher DC link voltage) will unavoidably increase the stress to the insulation system which leads to a decrease in reliability. Thus, a trade-off is required between power density and reliability during the machine design. Currently, it is a challenging task to evaluate reliability during the design stage and the over-engineering approach is applied. To solve this problem, physics of failure (POF) is introduced and its feasibility for electrical machine (EM) design is discussed through reviewing past work on insulation investigation. Then the special focus is given to partial discharge (PD) whose occurrence means the end-of-life of low-voltage EMs. The PD-free design methodology based on understanding the physics of PD is presented to substitute the over-engineering approach. Finally, a comprehensive reliability-oriented design (ROD) approach adopting POF and PD-free design strategy is given as a potential solution for reliable and high-performance inverter-fed low-voltage EM design.

scholarly journals Advanced Electrode Design for Low-Voltage High-Speed Thin-Film Lithium Niobate Modulators

2021 ◽  
Vol 13 (2) ◽  
pp. 1-9
Author(s):  
Xingrui Huang ◽  
Yang Liu ◽  
Zezheng Li ◽  
Huan Guan ◽  
Qingquan Wei ◽  
...  
Keyword(s):  
Thin Film ◽  
Lithium Niobate ◽  
High Speed ◽  
Low Voltage ◽  
Electrode Design

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

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