scholarly journals Memristor-CMOS Hybrid Circuit for Temporal-Pooling of Sensory and Hippocampal Responses of Cortical Neurons

Materials ◽  
2019 ◽  
Vol 12 (6) ◽  
pp. 875 ◽  
Author(s):  
Tien Nguyen ◽  
Khoa Pham ◽  
Kyeong-Sik Min
Keyword(s):  
Cortical Neurons ◽  
Hebbian Learning ◽  
Circuit Simulation ◽  
Sensory Information ◽  
Complementary Metal Oxide Semiconductor ◽  
External Noise ◽  
Oxide Semiconductor ◽  
Output Layer ◽  
Input Layer ◽  
Hybrid Circuit

As a software framework, Hierarchical Temporal Memory (HTM) has been developed to perform the brain’s neocortical functions, such as spatial and temporal pooling. However, it should be realized with hardware not software not only to mimic the neocortical function but also to exploit its architectural benefit. To do so, we propose a new memristor-CMOS (Complementary Metal-Oxide-Semiconductor) hybrid circuit of temporal-pooling here, which is composed of the input-layer and output-layer neurons mimicking the neocortex. In the hybrid circuit, the input-layer neurons have the proximal and basal/distal dendrites to combine sensory information with the temporal/location information from the brain’s hippocampus. Using the same crossbar architecture, the output-layer neurons can perform a prediction by integrating the temporal information on the basal/distal dendrites. For training the proposed circuit, we used only simple Hebbian learning, not the complicated backpropagation algorithm. Due to the simple hardware of Hebbian learning, the proposed hybrid circuit can be very suitable to online learning. The proposed memristor-CMOS hybrid circuit has been verified by the circuit simulation using the real memristor model. The proposed circuit has been verified to predict both the ordinal and out-of-order sequences. In addition, the proposed circuit has been tested with the external noise and memristance variation.

scholarly journals Neuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations

Materials ◽  
2019 ◽  
Vol 12 (17) ◽  
pp. 2745 ◽  
Author(s):  
Luis Camuñas-Mesa ◽  
Bernabé Linares-Barranco ◽  
Teresa Serrano-Gotarredona
Keyword(s):  
Neural Networks ◽  
Learning Strategies ◽  
Large Scale ◽  
Sensory Information ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Hardware Implementations ◽  
Learning Capabilities ◽  
Promising Solution

Inspired by biology, neuromorphic systems have been trying to emulate the human brain for decades, taking advantage of its massive parallelism and sparse information coding. Recently, several large-scale hardware projects have demonstrated the outstanding capabilities of this paradigm for applications related to sensory information processing. These systems allow for the implementation of massive neural networks with millions of neurons and billions of synapses. However, the realization of learning strategies in these systems consumes an important proportion of resources in terms of area and power. The recent development of nanoscale memristors that can be integrated with Complementary Metal–Oxide–Semiconductor (CMOS) technology opens a very promising solution to emulate the behavior of biological synapses. Therefore, hybrid memristor-CMOS approaches have been proposed to implement large-scale neural networks with learning capabilities, offering a scalable and lower-cost alternative to existing CMOS systems.

scholarly journals A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

2017 ◽  
Vol 7 (1) ◽  
Author(s):  
B. Chakrabarti ◽  
M. A. Lastras-Montaño ◽  
G. Adam ◽  
M. Prezioso ◽  
B. Hoskins ◽  
...  
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Switching Behavior ◽  
Molecular Architecture ◽  
Monolithically Integrated ◽  
Computing Paradigm ◽  
Memristor Crossbar ◽  
2D And 3D ◽  
Hybrid Circuit

Abstract Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

scholarly journals Hybrid Circuit of Memristor and Complementary Metal-Oxide-Semiconductor for Defect-Tolerant Spatial Pooling with Boost-Factor Adjustment

Materials ◽  
2019 ◽  
Vol 12 (13) ◽  
pp. 2122 ◽  
Author(s):  
Tien Van Nguyen ◽  
Khoa Van Pham ◽  
Kyeong-Sik Min
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Hierarchical Temporal Memory ◽  
Spatial Pooling ◽  
Boost Factor ◽  
Rate Loss ◽  
Memristor Synapse ◽  
Hybrid Circuit

Hierarchical Temporal Memory (HTM) has been known as a software framework to model the brain’s neocortical operation. However, mimicking the brain’s neocortical operation by not software but hardware is more desirable, because the hardware can not only describe the neocortical operation, but can also employ the brain’s architectural advantages. To develop a hybrid circuit of memristor and Complementary Metal-Oxide-Semiconductor (CMOS) for realizing HTM’s spatial pooler (SP) by hardware, memristor defects such as stuck-at-faults and variations should be considered. For solving the defect problem, we first show that the boost-factor adjustment can make HTM’s SP defect-tolerant, because the false activation of defective columns are suppressed. Second, we propose a memristor-CMOS hybrid circuit with the boost-factor adjustment to realize this defect-tolerant SP by hardware. The proposed circuit does not rely on the conventional defect-aware mapping scheme, which cannot avoid the false activation of defective columns. For the Modified subset of National Institute of Standards and Technology (MNIST) vectors, the boost-factor adjusted crossbar with defects = 10% shows a rate loss of only ~0.6%, compared to the ideal crossbar with defects = 0%. On the contrary, the defect-aware mapping without the boost-factor adjustment demonstrates a significant rate loss of ~21.0%. The energy overhead of the boost-factor adjustment is only ~0.05% of the programming energy of memristor synapse crossbar.

scholarly journals  Progress in the Triboelectric Human–Machine Interfaces (HMIs)-Moving from Smart Gloves to AI/Haptic Enabled HMI in the 5G/IoT Era

2021 ◽  
Vol 1 (1) ◽  
pp. 81-120
Author(s):  
Zhongda Sun ◽  
Minglu Zhu ◽  
Chengkuo Lee
Keyword(s):  
Smart Home ◽  
Haptic Feedback ◽  
Sensory Information ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Measurement Unit ◽  
Triboelectric Nanogenerator ◽  
Wearable Robot ◽  
Human Machine Interfaces ◽  
Self Powered

Entering the 5G and internet of things (IoT) era, human–machine interfaces (HMIs) capable of providing humans with more intuitive interaction with the digitalized world have experienced a flourishing development in the past few years. Although the advanced sensing techniques based on complementary metal-oxide-semiconductor (CMOS) or microelectromechanical system (MEMS) solutions, e.g., camera, microphone, inertial measurement unit (IMU), etc., and flexible solutions, e.g., stretchable conductor, optical fiber, etc., have been widely utilized as sensing components for wearable/non-wearable HMIs development, the relatively high-power consumption of these sensors remains a concern, especially for wearable/portable scenarios. Recent progress on triboelectric nanogenerator (TENG) self-powered sensors provides a new possibility for realizing low-power/self-sustainable HMIs by directly converting biomechanical energies into valuable sensory information. Leveraging the advantages of wide material choices and diversified structural design, TENGs have been successfully developed into various forms of HMIs, including glove, glasses, touchpad, exoskeleton, electronic skin, etc., for sundry applications, e.g., collaborative operation, personal healthcare, robot perception, smart home, etc. With the evolving artificial intelligence (AI) and haptic feedback technologies, more advanced HMIs could be realized towards intelligent and immersive human–machine interactions. Hence, in this review, we systematically introduce the current TENG HMIs in the aspects of different application scenarios, i.e., wearable, robot-related and smart home, and prospective future development enabled by the AI/haptic-feedback technology. Discussion on implementing self-sustainable/zero-power/passive HMIs in this 5G/IoT era and our perspectives are also provided.

scholarly journals Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits

Materials ◽  
2019 ◽  
Vol 12 (9) ◽  
pp. 1492 ◽  
Author(s):  
Yiming Li ◽  
Chieh-Yang Chen ◽  
Min-Hui Chuang ◽  
Pei-Jung Chao
Keyword(s):  
Metal Oxide ◽  
Power Consumption ◽  
Circuit Simulation ◽  
Short Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Computing System ◽  
Mobility Model ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Aspect Ratios

In this study, we investigate direct current (DC)/alternating current (AC) characteristic variability induced by work function fluctuation (WKF) with respect to different nanosized metal grains and the variation of aspect ratios (ARs) of channel cross-sections on a 10 nm gate gate-all-around (GAA) nanowire (NW) metal–oxide–semiconductor field-effect transistor (MOSFET) device. The associated timing and power fluctuations of the GAA NW complementary metal–oxide–semiconductor (CMOS) circuits are further estimated and analyzed simultaneously. The experimentally validated device and circuit simulation running on a parallel computing system are intensively performed while considering the effects of WKF and various ARs to access the device’s nominal and fluctuated characteristics. To provide the best accuracy of simulation, we herein calibrate the simulation results and experimental data by adjusting the fitting parameters of the mobility model. Transfer characteristics, dynamic timing, and power consumption of the tested circuit are calculated using a mixed device–circuit simulation technique. The timing fluctuation mainly follows the trend of the variation of threshold voltage. The fluctuation terms of power consumption comprising static, short-circuit, and dynamic powers are governed by the trend that the larger the grain size, the larger the fluctuation.

scholarly journals An E-Band 21-dB Variable-Gain Amplifier with 0.5-V Supply in 40-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 804
Author(s):  
Gibeom Shin ◽  
Kyunghwan Kim ◽  
Kangseop Lee ◽  
Hyun-Hak Jeong ◽  
Ho-Jin Song
Keyword(s):  
Power Consumption ◽  
Frequency Band ◽  
Noise Figure ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Operating Frequency ◽  
Variable Gain Amplifier ◽  
Variable Gain ◽  
Operating Frequency Band ◽  
Shunt Capacitors

This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3‑dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consumption per stage. Gate-bias control of the second stage in which feedback capacitances were neutralized with cross-coupled capacitors allowed us to vary the gain by around 21 dB in the operating frequency band. The noise figure was estimated to be better than 5.9 dB in the operating frequency band from the full electromagnetic (EM) simulation.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

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