scholarly journals 100 Gb/s Silicon Photonic WDM Transmitter with Misalignment-Tolerant Surface-Normal Optical Interfaces

Micromachines ◽  
2019 ◽  
Vol 10 (5) ◽  
pp. 336 ◽  
Author(s):  
Beiju Huang ◽  
Zanyun Zhang ◽  
Zan Zhang ◽  
Chuantong Cheng ◽  
Huang Zhang ◽  
...  

A 4 × 25 Gb/s ultrawide misalignment tolerance wavelength-division-multiplex (WDM) transmitter based on novel bidirectional vertical grating coupler has been demonstrated on complementary metal-oxide-semiconductor (CMOS)-compatible silicon-on-insulator (SOI) platform. Simulations indicate the bidirectional grating coupler (BGC) is widely misalignment tolerant, with an excess coupling loss of only 0.55 dB within ±3 μm fiber misalignment range. Measurement shows the excess coupling loss of the BGC is only 0.7 dB within a ±2 μm fiber misalignment range. The bidirectional grating structure not only functions as an optical coupler, but also acts as a beam splitter. By using the bidirectional grating coupler, the silicon optical modulator shows low insertion loss and large misalignment tolerance. The eye diagrams of the modulator at 25 Gb/s don’t show any obvious deterioration within the waveguide-direction fiber misalignment ranger of ±2 μm, and still open clearly when the misalignment offset is as large as ±4 μm.

Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.


Nanophotonics ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Feiying Sun ◽  
Changbin Nie ◽  
Xingzhan Wei ◽  
Hu Mao ◽  
Yupeng Zhang ◽  
...  

Abstract Two-dimensional (2D) materials with excellent optical properties and complementary metal-oxide-semiconductor (CMOS) compatibility have promising application prospects for developing highly efficient, small-scale all-optical modulators. However, due to the weak nonlinear light-material interaction, high power density and large contact area are usually required, resulting in low light modulation efficiency. In addition, the use of such large-band-gap materials limits the modulation wavelength. In this study, we propose an all-optical modulator integrated Si waveguide and single-layer MoS2 with a plasmonic nanoslit, wherein modulation and signal light beams are converted into plasmon through nanoslit confinement and together are strongly coupled to 2D MoS2. This enables MoS2 to absorb signal light with photon energies less than the bandgap, thereby achieving high-efficiency amplitude modulation at 1550 nm. As a result, the modulation efficiency of the device is up to 0.41 dB μm−1, and the effective size is only 9.7 µm. Compared with other 2D material-based all-optical modulators, this fabricated device exhibits excellent light modulation efficiency with a micron-level size, which is potential in small-scale optical modulators and chip-integration applications. Moreover, the MoS2-plasmonic nanoslit modulator also provides an opportunity for TMDs in the application of infrared optoelectronics.


Electronics ◽  
2019 ◽  
Vol 9 (1) ◽  
pp. 7
Author(s):  
Younghwan Bae ◽  
Heesauk Jhon ◽  
Junghyun Kim

In this paper, a novel coupler/reflection-type programmable electronic impedance tuner combined with switches that were fabricated by a 0.18-um complementary metal–oxide–semiconductor (CMOS) silicon-on-insulator (SOI) process is proposed for replacement of the conventional mechanical tuner in power amplifier (PA) load-pull test. By employing the multi-stacked field-effect transistors (FETs) as a single-branch switch, the proposed tuner has the advantage of precise impedance variation with systematic and magnitude and phase adjustment. Additionally, it led to high standing wave ratio (SWR) coverage and a good impedance resolution with a high power handling capability. Furthermore, the double-branch based on multi-stacked FET was applied to switches for additional enhancement of the intermodulation distortion (IMD) performance through the mitigated drain-source voltage of the single-FET. Drawing upon the measurement results, we demonstrated that SWR changed from 2 to 6 sequentially with a 12–15° phase angle step over a mid/high-band range of a 1.5–2.1 GHz band for 3G/4G handset application. In addition, the PA load-pull measurement results obtained using the proposed tuners verified their practicality and competitive performance with mechanical tuners. Finally, the measured linearity using the double-branch switch demonstrated the good IMD3 performance of −78 dBc, and this result is noteworthy when compared with conventional electronic impedance tuners.


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