scholarly journals All-optical modulation based on MoS2-Plasmonic nanoslit hybrid structures

Nanophotonics ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Feiying Sun ◽  
Changbin Nie ◽  
Xingzhan Wei ◽  
Hu Mao ◽  
Yupeng Zhang ◽  
...  
Keyword(s):  
High Efficiency ◽  
Single Layer ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Optical Modulator ◽  
Small Scale ◽  
Light Modulation ◽  
Optical Modulators ◽  
Signal Light ◽  
All Optical

Abstract Two-dimensional (2D) materials with excellent optical properties and complementary metal-oxide-semiconductor (CMOS) compatibility have promising application prospects for developing highly efficient, small-scale all-optical modulators. However, due to the weak nonlinear light-material interaction, high power density and large contact area are usually required, resulting in low light modulation efficiency. In addition, the use of such large-band-gap materials limits the modulation wavelength. In this study, we propose an all-optical modulator integrated Si waveguide and single-layer MoS2 with a plasmonic nanoslit, wherein modulation and signal light beams are converted into plasmon through nanoslit confinement and together are strongly coupled to 2D MoS2. This enables MoS2 to absorb signal light with photon energies less than the bandgap, thereby achieving high-efficiency amplitude modulation at 1550 nm. As a result, the modulation efficiency of the device is up to 0.41 dB μm−1, and the effective size is only 9.7 µm. Compared with other 2D material-based all-optical modulators, this fabricated device exhibits excellent light modulation efficiency with a micron-level size, which is potential in small-scale optical modulators and chip-integration applications. Moreover, the MoS2-plasmonic nanoslit modulator also provides an opportunity for TMDs in the application of infrared optoelectronics.

scholarly journals Analysis of Optical Integration between Si3N4 Waveguide and a Ge-Based Optical Modulator Using a Lateral Amorphous GeSi Taper at the Telecommunication Wavelength of 1.55 µm

2019 ◽  
Vol 9 (18) ◽  
pp. 3846
Author(s):  
Worawat Traiwattanapong ◽  
Kazumi Wada ◽  
Papichaya Chaisakul
Keyword(s):  
Low Voltage ◽  
Extinction Ratio ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Fdtd Simulation ◽  
Optical Modulator ◽  
Optical Modulators ◽  
Optical Wavelength ◽  
Mode Size ◽  
Small Footprint

We report on the theoretical investigation of using an amorphous Ge0.83Si0.17 lateral taper to enable a low-loss small-footprint optical coupling between a Si3N4 waveguide and a low-voltage Ge-based Franz–Keldysh optical modulator on a bulk Si substrate using 3D Finite-Difference Time-Domain (3D-FDTD) simulation at the optical wavelength of 1550 nm. Despite a large refractive index and optical mode size mismatch between Si3N4 and the Ge-based modulator, the coupling structure rendered a good coupling performance within fabrication tolerance of advanced complementary metal-oxide semiconductor (CMOS) processes. For integrated optical modulator performance, the Si3N4-waveguide-integrated Ge-based on Si optical modulators could simultaneously provide workable values of extinction ratio (ER) and insertion loss (IL) for optical interconnect applications with a compact footprint.

scholarly journals Complete Ring Artifacts Reduction Procedure for Lab-Based X-ray Nano CT Systems

Sensors ◽  
2021 ◽  
Vol 21 (1) ◽  
pp. 238
Author(s):  
Jakub Šalplachta ◽  
Tomáš Zikmund ◽  
Marek Zemek ◽  
Adam Břínek ◽  
Yoshihiro Takeda ◽  
...  
Keyword(s):  
High Efficiency ◽  
Image Inpainting ◽  
Simulated Data ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Detection Accuracy ◽  
Reduction Procedure ◽  
X Ray ◽  
Artifacts Reduction ◽  
Ct Data

In this article, we introduce a new ring artifacts reduction procedure that combines several ideas from existing methods into one complex and robust approach with a goal to overcome their individual weaknesses and limitations. The procedure differentiates two types of ring artifacts according to their cause and character in computed tomography (CT) data. Each type is then addressed separately in the sinogram domain. The novel iterative schemes based on relative total variations (RTV) were integrated to detect the artifacts. The correction process uses the image inpainting, and the intensity deviations smoothing method. The procedure was implemented in scope of lab-based X-ray nano CT with detection systems based on charge-coupled device (CCD) and scientific complementary metal–oxide–semiconductor (sCMOS) technologies. The procedure was then further tested and optimized on the simulated data and the real CT data of selected samples with different compositions. The performance of the procedure was quantitatively evaluated in terms of the artifacts’ detection accuracy, the comparison with existing methods, and the ability to preserve spatial resolution. The results show a high efficiency of ring removal and the preservation of the original sample’s structure.

A new approach to bypass wire crossing problem in QCA nano technology

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Ali Majeed ◽  
Esam Alkaldy
Keyword(s):  
Power Dissipation ◽  
Single Layer ◽  
Complementary Metal Oxide Semiconductor ◽  
Full Adder ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Nano Technology ◽  
New Approach ◽  
Content Type ◽  
Wire Crossing

Purpose This study aims to replace current multi-layer and coplanar wire crossing methods in QCA technology to avoid fabrication difficulties caused by them. Design/methodology/approach Quantum-dot cellular automata (QCA) is one of the newly emerging nanoelectronics technology tools that is proposed as a good replacement for complementary metal oxide semiconductor (CMOS) technology. This technology has many challenges, among them being component interconnection and signal routing. This paper will propose a new wire crossing method to enhance layout use in a single layer. The presented method depends on the central cell clock phase to enable two signals to cross over without interference. QCADesigner software is used to simulate a full adder circuit designed with the proposed wire crossing method to be used as a benchmark for further analysis of the presented wire crossing approach. QCAPro software is used for power dissipation analysis of the proposed adder. Findings A new cost function is presented in this paper to draw attention to the fabrication difficulties of the technology when designing QCA circuits. This function is applied to the selected benchmark circuit, and the results show good performance of the proposed method compared to others. The improvement is around 59, 33 and 75% compared to the best reported multi-layer wire crossing, coplanar wire crossing and logical crossing, respectively. The power dissipation analysis shows that the proposed method does not cause any extra power consumption in the circuit. Originality/value In this paper, a new approach is developed to bypass the wire crossing problem in the QCA technique.

scholarly journals Implementation of Unbalanced Ternary Logic Gates with the Combination of Spintronic Memristor and CMOS

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 542 ◽  
Author(s):  
Haifeng Zhang ◽  
Zhaowei Zhang ◽  
Mingyu Gao ◽  
Li Luo ◽  
Shukai Duan ◽  
...  
Keyword(s):  
High Efficiency ◽  
Load Capacity ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Logic Circuit ◽  
Oxide Semiconductor ◽  
Ternary Logic ◽  
Logic Operations ◽  
Almost All ◽  
Logic Functions

A memristor is a nanoscale electronic element that displays a threshold property, non-volatility, and variable conductivity. Its composite circuits are promising for the implementation of intelligence computation, especially for logic operations. In this paper, a flexible logic circuit composed of a spintronic memristor and complementary metal-oxide-semiconductor (CMOS) switches is proposed for the implementation of the basic unbalanced ternary logic gates, including the NAND, NOR, AND, and OR gates. Meanwhile, due to the participation of the memristor and CMOS, the proposed circuit has advantages in terms of non-volatility and load capacity. Furthermore, the input and output of the proposed logic are both constant voltages without signal degradation. All these three merits make the proposed circuit capable of realizing the cascaded logic functions. In order to demonstrate the validity and effectiveness of the entire work, series circuit simulations were carried out. The experimental results indicated that the proposed logic circuit has the potential to realize almost all basic ternary logic gates, and even some more complicated cascaded logic functions with a compact circuit construction, high efficiency, and good robustness.

scholarly journals 100 Gb/s Silicon Photonic WDM Transmitter with Misalignment-Tolerant Surface-Normal Optical Interfaces

Micromachines ◽  
2019 ◽  
Vol 10 (5) ◽  
pp. 336 ◽  
Author(s):  
Beiju Huang ◽  
Zanyun Zhang ◽  
Zan Zhang ◽  
Chuantong Cheng ◽  
Huang Zhang ◽  
...  
Keyword(s):  
Wavelength Division Multiplex ◽  
Complementary Metal Oxide Semiconductor ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Optical Modulator ◽  
Grating Coupler ◽  
Coupling Loss ◽  
Wavelength Division ◽  
Silicon Photonic ◽  
Fiber Misalignment

A 4 × 25 Gb/s ultrawide misalignment tolerance wavelength-division-multiplex (WDM) transmitter based on novel bidirectional vertical grating coupler has been demonstrated on complementary metal-oxide-semiconductor (CMOS)-compatible silicon-on-insulator (SOI) platform. Simulations indicate the bidirectional grating coupler (BGC) is widely misalignment tolerant, with an excess coupling loss of only 0.55 dB within ±3 μm fiber misalignment range. Measurement shows the excess coupling loss of the BGC is only 0.7 dB within a ±2 μm fiber misalignment range. The bidirectional grating structure not only functions as an optical coupler, but also acts as a beam splitter. By using the bidirectional grating coupler, the silicon optical modulator shows low insertion loss and large misalignment tolerance. The eye diagrams of the modulator at 25 Gb/s don’t show any obvious deterioration within the waveguide-direction fiber misalignment ranger of ±2 μm, and still open clearly when the misalignment offset is as large as ±4 μm.

Analog Complementary Metal–Oxide–Semiconductor Integrate-and-Fire Neuron Circuit for Overflow Retaining in Hardware Spiking Neural Networks

2020 ◽  
Vol 20 (5) ◽  
pp. 3117-3122
Author(s):  
Sungmin Hwang ◽  
Jeong-Jun Lee ◽  
Min-Woo Kwon ◽  
Myung-Hyun Baek ◽  
Taejin Jang ◽  
...  
Keyword(s):  
Neural Network ◽  
High Performance ◽  
Single Layer ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Basic Operation ◽  
Neuron Circuit ◽  
Integrate And Fire ◽  
Analog Cmos ◽  
High Level

The spiking neural network (SNN) is regarded as the third generation of an artificial neural network (ANN). In order to realize a high-performance SNN, an integrate-and-fire (I&F) neuron, one of the key elements in an SNN, must retain the overflow in its membrane after firing. This paper presents an analog CMOS I&F neuron circuit for overflow retaining. Compared with the conventional I&F neuron circuit, the basic operation of the proposed circuit is confirmed in a circuit-level simulation. Furthermore, a single-layer SNN simulation was also performed to demonstrate the effect of the proposed circuit on neural network applications by comparing the raster plots from the circuit-level simulation with those from a high-level simulation. These results demonstrate the potential of the I&F neuron circuit with overflow retaining characteristics to be utilized in upcoming high-performance hardware SNN systems.

scholarly journals Electro-Absorption Modulation in GeSn Alloys for Wide-Spectrum Mid-Infrared Applications

2021 ◽  
Author(s):  
Yun-Da Hsieh ◽  
Jun-Han Lin ◽  
Richard Soref ◽  
Greg Sun ◽  
Hung-Hsiang Cheng ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Wide Spectrum ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Optical Modulation ◽  
Bandgap Energy ◽  
Optical Modulators ◽  
Mid Infrared ◽  
Wide Range ◽  
On Chip

Abstract Si-based electronic-photonic integrated circuits (EPICs), which are compatible with state-of-the-art complementary metal-oxide-semiconductor (CMOS) processes, offer promising opportunities for on-chip mid-infrared (MIR) photonic systems. However, the lack of efficient MIR optical modulators on Si hinders the utilization of MIR EPICs. Here, we clearly demonstrate the Franz-Keldysh (FK) effect in GeSn alloys and achieve on-Si MIR electro-absorption optical modulation using GeSn heterostructures. Our experimental and theoretical results verify that the direct bandgap energy of GeSn can be widely tuned by varying the Sn content, thereby realizing wavelength-tunable optical modulation in the MIR range with a figure-of-merit of Δα /α0 (FOM) greater than 1.5 and a broadband operating range greater than 140 nm. In contrast to conventional silicon-photonic modulators based on the plasma dispersion effect, our GeSn heterostructure demonstrates practical and effective FK MIR optical modulation on Si and helps unlock the potential of MIR EPICs for a wide range of applications.

Easily Cascaded Memristor-CMOS Hybrid Circuit for High-Efficiency Boolean Logic Implementation

2018 ◽  
Vol 28 (12) ◽  
pp. 1850149 ◽  
Author(s):  
Zhekang Dong ◽  
Donglian Qi ◽  
Yufei He ◽  
Zhao Xu ◽  
Xiaofang Hu ◽  
...  
Keyword(s):  
High Efficiency ◽  
Operating Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Boolean Logic ◽  
Oxide Semiconductor ◽  
Total Delay ◽  
Switching Dynamics ◽  
Two Phases ◽  
Logic Operations

Memristor is a novel passive electronic element with resistance-switching dynamics. Due to the threshold property and the variable conductivity of the memristive element, its composite circuits are promising for the implementation of logic operations. In this paper, a flexible logic circuit based on the threshold-type memristor and the mature complementary metal-oxide-semiconductor (CMOS) technology is designed for the realization of Boolean logic operations. Specifically, the proposed method is able to perform the NAND, AND, OR, and NOR gate operations through two phases, i.e. the writing operation and the reading operation. In such implementation, the total delay is very small especially for time-sequence inputs. Furthermore, for existing memristor-based logic implementation, a contrastive analysis with relevant computer simulations is carried out. The experimental results indicate that the proposed method is capable of realizing all basic Boolean logic operations, and some more complicated cascaded logic operations with more compact circuit structures, higher efficiency, and lower operating cost.

scholarly journals Online Nonlinear Error Compensation Circuit Based on Neural Networks

Machines ◽  
2021 ◽  
Vol 9 (8) ◽  
pp. 151
Author(s):  
Zhenyi Gao ◽  
Bin Zhou ◽  
Chunge Ju ◽  
Qi Wei ◽  
Xinxi Zhang ◽  
...  
Keyword(s):  
Machine Learning ◽  
Neural Networks ◽  
Power Consumption ◽  
Inertial Sensors ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Signal Frequency ◽  
Small Scale ◽  
Compensation Circuit

Nonlinear errors of sensor output signals are common in the field of inertial measurement and can be compensated with statistical models or machine learning models. Machine learning solutions with large computational complexity are generally offline or implemented on additional hardware platforms, which are difficult to meet the high integration requirements of microelectromechanical system inertial sensors. This paper explored the feasibility of an online compensation scheme based on neural networks. In the designed solution, a simplified small-scale network is used for modeling, and the peak-to-peak value and standard deviation of the error after compensation are reduced to 17.00% and 16.95%, respectively. Additionally, a compensation circuit is designed based on the simplified modeling scheme. The results show that the circuit compensation effect is consistent with the results of the algorithm experiment. Under SMIC 180 nm complementary metal-oxide semiconductor (CMOS) technology, the circuit has a maximum operating frequency of 96 MHz and an area of 0.19 mm2. When the sampling signal frequency is 800 kHz, the power consumption is only 1.12 mW. This circuit can be used as a component of the measurement and control system on chip (SoC), which meets real-time application scenarios with low power consumption requirements.

scholarly journals Photoluminescence enhancement by deterministically site-controlled, vertically stacked SiGe quantum dots

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Jeffrey Schuster ◽  
Johannes Aberl ◽  
Lada Vukušić ◽  
Lukas Spindlberger ◽  
Heiko Groiss ◽  
...  
Keyword(s):  
Light Emission ◽  
Thermal Quenching ◽  
Single Layer ◽  
Complementary Metal Oxide Semiconductor ◽  
Strain Engineering ◽  
Nucleation Site ◽  
Oxide Semiconductor ◽  
Light Sources ◽  
Indirect Band Gap ◽  
Sige Quantum Dot

AbstractThe Si/SiGe heterosystem would be ideally suited for the realization of complementary metal-oxide-semiconductor (CMOS)-compatible integrated light sources, but the indirect band gap, exacerbated by a type-II band offset, makes it challenging to achieve efficient light emission. We address this problem by strain engineering in ordered arrays of vertically close-stacked SiGe quantum dot (QD) pairs. The strain induced by the respective lower QD creates a preferential nucleation site for the upper one and strains the upper QD as well as the Si cap above it. Electrons are confined in the strain pockets in the Si cap, which leads to an enhanced wave function overlap with the heavy holes near the upper QD’s apex. With a thickness of the Si spacer between the stacked QDs below 5 nm, we separated the functions of the two QDs: The role of the lower one is that of a pure stressor, whereas only the upper QD facilitates radiative recombination of QD-bound excitons. We report on the design and strain engineering of the QD pairs via strain-dependent Schrödinger-Poisson simulations, their implementation by molecular beam epitaxy, and a comprehensive study of their structural and optical properties in comparison with those of single-layer SiGe QD arrays. We find that the double QD arrangement shifts the thermal quenching of the photoluminescence signal at higher temperatures. Moreover, detrimental light emission from the QD-related wetting layers is suppressed in the double-QD configuration.

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