Binary Addition in Resistance Switching Memory Array by Sensing Majority

The flow of data between processing and memory units in contemporary computing systems is their main performance and energy-efficiency bottleneck, often referred to as the ‘von Neumann bottleneck’ or ‘memory wall’. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic, and in many nanotechnologies, it has been found to be an efficient logic primitive. In this paper, a technique is proposed to implement a majority gate in a memory array. The majority gate is realised in an energy-efficient manner as a memory R E A D operation. The proposed logic family disintegrates arithmetic operations to majority and NOT operations which are implemented as memory R E A D and W R I T E operations. A 1-bit full adder can be implemented in 6 steps (memory cycles) in a 1T–1R array, which is faster than I M P L Y , N A N D , N O R and other similar logic primitives.

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Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea10030028 ◽

2020 ◽

Vol 10 (3) ◽

pp. 28

Author(s):

John Reuben

Keyword(s):

Integrated Circuits ◽

Logic Gates ◽

Expressive Power ◽

Boolean Logic ◽

Majority Gate ◽

Von Neumann ◽

Majority Logic ◽

Memory Array ◽

Memory Wall ◽

Parallel Prefix

As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives.

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Reconfigurable nonvolatile boolean logic with one-transistor-two-memristor for in-memory computing

Semiconductor Science and Technology ◽

10.1088/1361-6641/ac363b ◽

2021 ◽

Author(s):

Ziling Wang ◽

Li Luo ◽

Jie Li ◽

Lidan Wang ◽

shukai duan

Keyword(s):

Large Scale ◽

Full Adder ◽

Boolean Logic ◽

Device Structure ◽

Von Neumann ◽

Computing Paradigm ◽

Operation Process ◽

Strong Candidate ◽

High Flexibility ◽

Logic Functions

Abstract In-memory computing is highly expected to break the von Neumann bottleneck and memory wall. Memristor with inherent nonvolatile property is considered to be a strong candidate to execute this new computing paradigm. In this work, we have presented a reconfigurable nonvolatile logic method based on one-transistor-two-memristor (1T2M) device structure, inhibiting the sneak path in the large-scale crossbar array. By merely adjusting the applied voltage signals, all 16 binary Boolean logic functions can be achieved in a single cell. More complex computing tasks including one-bit parallel full adder and Set-Reset latch have also been realized with optimization, showing simple operation process, high flexibility, and low computational complexity. The circuit verification based on cadence PSpice simulation is also provided, proving the feasibility of the proposed design. The work in this paper is intended to make progress in constructing architectures for in-memory computing paradigm.

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Performance evaluation of an efficient five input majority gate design in QCA nanotechnology

International Journal of Reconfigurable and Embedded Systems (IJRES) ◽

10.11591/ijres.v8.i3.pp194-205 ◽

2019 ◽

Vol 8 (3) ◽

pp. 194

Author(s):

Amanpreet Sandhu ◽

Sheifali Gupta

Keyword(s):

Energy Efficiency ◽

Performance Evaluation ◽

Power Dissipation ◽

Energy Efficient ◽

High Speed ◽

Clock Cycle ◽

Full Adder ◽

Majority Gate ◽

Quantum Dot Cellular Automata ◽

Gate Count

Quantum-dot-cellular-automata (QCA) is the imminent transistor less technology, considered at nano level with high speed of operation and lower power dissipation features. The present paper proposes a novel and an efficient 5-input coplanar majority gate (PMG) with improved structural and energy efficiency. The proposed gate consumes an occupational area of 0.01μm2 with 17 QCA cells which is 50% less in comparison to the best designs reported in literature. The proposed structure is also more energy efficient because it dissipates 21.1% less energy than the best reported designs. The correctness of a proposed majority gate is verified by designing a single bit full adder. The new 1-bit full adder design is structural efficient and robust in terms of gate count and clock delay. It consumes occupational area of 0.05μm2 with 58 QCA cells showing 16.6% improvement in structural efficiency as compared to the best design reported in. It is having a gate count of 4 with the delay of 1 clock cycle. Here, the QCADesigner and QCAPro tools are utilized for the simulation and energy dissipation analysis of proposed majority gate and full adder design.

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Ultra‐low‐voltage GDI‐based hybrid full adder design for area and energy‐efficient computing systems

IET Circuits Devices & Systems ◽

10.1049/iet-cds.2018.5559 ◽

2019 ◽

Vol 13 (4) ◽

pp. 465-470 ◽

Cited By ~ 4

Author(s):

Kishore Sanapala ◽

Ramachandran Sakthivel

Keyword(s):

Energy Efficient ◽

Low Voltage ◽

Full Adder ◽

Computing Systems ◽

Energy Efficient Computing

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All-optical majority gate based on an injection-locked laser

Scientific Reports ◽

10.1038/s41598-019-51025-y ◽

2019 ◽

Vol 9 (1) ◽

Cited By ~ 2

Author(s):

Tuomo von Lerber ◽

Matti Lassas ◽

Vladimir S. Lyubopytov ◽

Lauri Ylinen ◽

Arkadi Chipouline ◽

...

Keyword(s):

Full Adder ◽

Boolean Logic ◽

Rate Equations ◽

Cavity Surface ◽

Optical Processing ◽

Majority Gate ◽

Ripple Carry Adder ◽

All Optical ◽

Bit Error Ratio ◽

Signal Encoding

Abstract An all-optical computer has remained an elusive concept. To construct a practical computing primitive equivalent to an electronic Boolean logic, one should utilize nonlinearity that overcomes weaknesses that plague many optical processing schemes. An advantageous nonlinearity provides a complete set of logic operations and allows cascaded operations without changes in wavelength or in signal encoding format. Here we demonstrate an all-optical majority gate based on a vertical-cavity surface-emitting laser (VCSEL). Using emulated signal coupling, the arrangement provides Bit Error Ratio (BER) of 10−6 at the rate of 1 GHz without changes in the wavelength or in the signal encoding format. Cascaded operation of the injection-locked laser majority gate is simulated on a full adder and a 3-bit ripple-carry adder circuits. Finally, utilizing the spin-flip model semiconductor laser rate equations, we prove that injection-locked lasers may perform normalization operations in the steady-state with an arbitrary linear state of polarization.

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Design of In-Memory Parallel-Prefix Adders

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea11040045 ◽

2021 ◽

Vol 11 (4) ◽

pp. 45

Author(s):

John Reuben

Keyword(s):

Computer Arithmetic ◽

Boolean Logic ◽

Von Neumann ◽

Majority Logic ◽

Memory Array ◽

Emerging Memory ◽

Non Volatile Memory ◽

Parallel Prefix ◽

Prefix Adder ◽

Prefix Adders

Computational methods in memory array are being researched in many emerging memory technologies to conquer the ‘von Neumann bottleneck’. Resistive RAM (ReRAM) is a non-volatile memory, which supports Boolean logic operation, and adders can be implemented as a sequence of Boolean operations in the memory. While many in-memory adders have recently been proposed, their latency is exorbitant for increasing bit-width (O(n)). Decades of research in computer arithmetic have proven parallel-prefix technique to be the fastest addition technique in conventional CMOS-based binary adders. This work endeavors to move parallel-prefix addition to the memory array to significantly minimize the latency of in-memory addition. Majority logic was chosen as the fundamental logic primitive and parallel-prefix adders synthesized in majority logic were mapped to the memory array using the proposed algorithm. The proposed algorithm can be used to map any parallel-prefix adder to a memory array and mapping is performed in such a way that the latency of addition is minimized. The proposed algorithm enables addition in O(log(n)) latency in the memory array.

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A Neural Network Decomposition Algorithm for Mapping on Crossbar-Based Computing Systems

Electronics ◽

10.3390/electronics9091526 ◽

2020 ◽

Vol 9 (9) ◽

pp. 1526 ◽

Cited By ~ 1

Author(s):

Choongmin Kim ◽

Jacob A. Abraham ◽

Woochul Kang ◽

Jaeyong Chung

Keyword(s):

Neural Network ◽

Neural Networks ◽

Predictive Performance ◽

Fixed Number ◽

Decomposition Algorithm ◽

Computing Systems ◽

Network Decomposition ◽

Von Neumann ◽

Analog Computing ◽

The Neural Network

Crossbar-based neuromorphic computing to accelerate neural networks is a popular alternative to conventional von Neumann computing systems. It is also referred as processing-in-memory and in-situ analog computing. The crossbars have a fixed number of synapses per neuron and it is necessary to decompose neurons to map networks onto the crossbars. This paper proposes the k-spare decomposition algorithm that can trade off the predictive performance against the neuron usage during the mapping. The proposed algorithm performs a two-level hierarchical decomposition. In the first global decomposition, it decomposes the neural network such that each crossbar has k spare neurons. These neurons are used to improve the accuracy of the partially mapped network in the subsequent local decomposition. Our experimental results using modern convolutional neural networks show that the proposed method can improve the accuracy substantially within about 10% extra neurons.

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