scholarly journals Modeling of Statistical Variation Effects on DRAM Sense Amplifier Offset Voltage

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1145
Author(s):  
Kyung Min Koo ◽  
Woo Young Chung ◽  
Sang Yi Lee ◽  
Gyu Han Yoon ◽  
Woo Young Choi
Keyword(s):  
Random Access ◽  
Critical Factor ◽  
Random Access Memory ◽  
Test Point ◽  
Access Memory ◽  
Sense Amplifier ◽  
Offset Voltage ◽  
Statistical Variation ◽  
Sense Amplifiers ◽  
First Time

With the downscaling in device sizes, process-induced parameter variation has emerged as one of the most serious problems. In particular, the parameter fluctuation of the dynamic random access memory (DRAM) sense amplifiers causes an offset voltage, leading to sensing failure. Previous studies indicate that the threshold voltage mismatch between the paired transistors of a sense amplifier is the most critical factor. In this study, virtual wafers were generated, including statistical VT variation. Then, we numerically investigate the prediction accuracy and reliability of the offset voltage of DRAM wafers using test point measurement for the first time. We expect that this study will be helpful in strengthening the in-line controllability of wafers to secure the DRAM sensing margin.

scholarly journals Design and Analysis of Low Power 4T Sense Amplifier with Capacitive Offset Correction

2020 ◽  
Vol 9 (4) ◽  
pp. 1536-1543
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Literature Survey ◽  
Static Random Access Memory ◽  
Small Signal ◽  
Access Memory ◽  
Sense Amplifier ◽  
Offset Correction ◽  
Power And Energy ◽  
Operational Block

In this paper Sense Amplifier is analyzed the basic and fundamental operational block in the Static Random Access Memory. The function of the sense amplifier is to amplify the small signal bit line voltages into high voltages. In the existing literature survey, there are many methods available for designing the sense amplifier. In this paper, the cross-coupled sense amplifier is modified into a 4T based sense amplifier. The proposed scheme also developed for capacitive offset correction based sense amplifier. The existing and proposed designs of SA are briefly examined in this paper. The proposed design is implemented in the linear predictive technology model. The parameters like power and energy. The proposed scheme shows the better results compared to the existing method.

scholarly journals A new dual asymmetric bit-line sense amplifier for low-voltage dynamic random access memory

2013 ◽  
Vol 10 (18) ◽  
pp. 20130647-20130647 ◽  
Author(s):  
Kyong Jun Noh ◽  
Jung Han Kim ◽  
Cheol Ha Lee ◽  
Jun Dong Cho
Keyword(s):  
Low Voltage ◽  
Random Access ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
Sense Amplifier

Soft Single-Bit Failure on Power Fluctuation by Concurrent Operation

2018 ◽  
Author(s):  
Keunchul Ryu ◽  
Incheol Nam ◽  
Jinseon Kim ◽  
Daesun Kim ◽  
Hongsun Hwang ◽  
...  
Keyword(s):  
Noise Analysis ◽  
Random Access ◽  
Random Access Memory ◽  
Soft Or ◽  
Access Memory ◽  
Voltage Fluctuation ◽  
Power Fluctuation ◽  
Sense Amplifier ◽  
Dimensional Shrinkage ◽  
Random Failures

Abstract Reduced noise immunity due to dimensional shrinkage, lower operational voltages and increasing densities results in increased soft or random failures. In practice, noises are generated by complex operation of device. In Dynamic Random Access Memory (DRAM), failures by noise are regarded as either decrease in charge at cell capacitor or increase in systematic interferences. Simple equivalent circuit of One Transistor One Capacitor (1T1C) DRAM and theoretical approach in time-domain are provided for quantitative noise analysis related to sense amplifier circuitries. Results show that local voltage fluctuation reduces sensing margin to judge data-0 or data-1. This phenomenon is easily observed at 1T1C with high resistance because response of voltage generator is comparatively slow.

High-temperature Process Endurance of Oxide/Electrode Stacking Structure for Resistance Random Access Memory

2010 ◽  
Vol 1250 ◽  
Author(s):  
Hisashi Shima ◽  
Takashi Nakano ◽  
Hiro Akinaga
Keyword(s):  
Oxygen Potential ◽  
Electrode Materials ◽  
Random Access ◽  
Critical Factor ◽  
Random Access Memory ◽  
High Resistance State ◽  
Systematic Investigation ◽  
Access Memory ◽  
Resistance Random Access Memory ◽  
Stacking Structure

AbstractThe systematic investigation on the thermal stability of the CoO layer was carried out for various electrode materials. When Pt with higher oxygen potential (Gibbs free energy change of the oxidation reaction) compared to Co is used as electrodes, the resistance of the Pt/CoO/Pt devise was severely decreased by the post deposition annealing (PDA) process and the resistance switching into the high resistance state was observed in the first voltage sweep. This indicants that the reducing Ar ambient induces the quite local reduction of CoO. The reduction of the CoO layer is also expected even with the Co electrode, which is reasonably attributed to the oxygen concentration gradient at the Co/CoO interface in the Co/CoO/Pt device. With the Ti electrode having a much lower oxygen potential than Co, the reduction of CoO by Ti is also indicated electrically in the Pt/CoO/Ti device. On the other hands, W electrodes which is thought to have the solid-solution oxygen can stabilize the CoO layer during PDA although W is more affinitive with oxygen compared with Co. It can be pointed out the oxygen delivery at the electrode/oxide layer interface is a critical factor in designing the thermally stable stacking structure for resistance random access memory.

Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

1998 ◽  
Author(s):  
Phil Schani ◽  
S. Subramanian ◽  
Vince Soorholtz ◽  
Pat Liston ◽  
Jamey Moss ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Temperature Sensitive ◽  
Wafer Level ◽  
Top Down ◽  
Access Memory ◽  
Transmission Electron ◽  
Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

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