scholarly journals A 20–44 GHz Wideband LNA Design Using the SiGe Technology for 5G Millimeter-Wave Applications

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1520
Author(s):  
Warsha Balani ◽  
Mrinal Sarvagya ◽  
Tanweer Ali ◽  
Ajit Samasgikar ◽  
Pradeep Kumar ◽  
...  
Keyword(s):  
Reflection Coefficient ◽  
Millimeter Wave ◽  
Frequency Band ◽  
Transmission Lines ◽  
Silicon Germanium ◽  
Noise Figure ◽  
Low Noise ◽  
Input Matching ◽  
Noise Amplifier ◽  
Bond Pads

This paper presents the design and implementation of a low-noise amplifier (LNA) for millimeter-wave (mm-Wave) 5G wireless applications. The LNA was based on a common-emitter configuration with cascode amplifier topology using an IHP’s 0.13 μm Silicon Germanium (SiGe) heterojunction bipolar transistor (HBT) whose f_T/f_MAX/gate-delay is 360/450 GHz/2.0 ps, utilizing transmission lines for simultaneous noise and input matching. A noise figure of 3.02–3.4 dB was obtained for the entire wide bandwidth from 20 to 44 GHz. The designed LNA exhibited a gain (S_21) greater than 20 dB across the 20–44 GHz frequency range and dissipated 9.6 mW power from a 1.2 V supply. The input reflection coefficient (S_11) and output reflection coefficient (S_22) were below −10 dB, and reverse isolation (S_12) was below −55 dB for the 20–44 GHz frequency band. The input 1 dB (P1dB) compression point of −18 dBm at 34.5 GHz was obtained. The proposed LNA occupies only a 0.715 mm2 area, with input and output RF (Radio Frequency) bond pads. To the authors’ knowledge, this work evidences the lowest noise figure, lowest power consumption with reasonable highest gain, and highest bandwidth attained so far at this frequency band in any silicon-based technology.

A 3.1~10.6 Ghz Ultra-Wideband SiGe Low Noise Amplifier with Current-Reused Technique

2011 ◽  
Vol 130-134 ◽  
pp. 3251-3254
Author(s):  
Kang Li ◽  
Chi Liu ◽  
Xiao Feng Yang ◽  
Qian Feng ◽  
Chao Xian Zhu ◽  
...  
Keyword(s):  
Reflection Coefficient ◽  
Silicon Germanium ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Total Power ◽  
Input Matching ◽  
Total Power Consumption ◽  
Noise Amplifier

A 3.1 ~ 10.6 GHz Ultra-Wideband SiGe Low Noise Amplifier (LNA) is proposed. This low noise amplifier utilizes a current-reused technique to increase the gain and extend the bandwidth. We have a detailed analysis for the input matching, noise figure, gain and other features. The LNA was designed with the TSMC 0.35µm bipolar silicon-germanium (SiGe) processes. Simulation results show that the input reflection coefficient is less than-9dB, the output reflection coefficient is less than-10dB, the maximum power gain of 17 dB and the minimum noise factor (NF) of 2.35dB. The total power consumption is 6.2 mW with 2.5V power supply.

Inductive Feedback Technique for Design of High Gain 0.18μm CMOS LNA for 5G Applications

2021 ◽  
pp. 2150236
Author(s):  
Anjana Jyothi Banu ◽  
G. Kavya ◽  
D. Jahnavi
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Common Source ◽  
Matching Network ◽  
Input Matching ◽  
Cmos Lna ◽  
Noise Amplifier

A 26[Formula: see text]GHz low-noise amplifier (LNA) designed for 5G applications using 0.18[Formula: see text][Formula: see text]m CMOS technology is proposed in this paper. The circuit includes a common-source in the first stage to suppress the noise in the amplifier. The successive stage has a Cascode topology along with an inductive feedback to improve the power gain. The input matching network is designed to achieve the input reflection coefficient less than [Formula: see text]7dB at the intended frequency. The matching network at the output is designed using inductor–capacitor (LC) components connected in parallel to attain the output reflection coefficient of [Formula: see text]10[Formula: see text]dB. Due to the inductor added in feedback at the second stage. The [Formula: see text] obtained is 18.208[Formula: see text]dB at 26[Formula: see text]GHz with a noise figure (NF) of 2.8[Formula: see text]dB. The power supply given to the LNA is 1.8[Formula: see text]V. The simulation and layout of the presented circuit are performed using Cadence Virtuoso software.

A 5.7 mW, UWB LNA for Wireless Applications Using Noise Canceling Technique in 90 nm CMOS

Frequenz ◽  
2020 ◽  
Vol 74 (1-2) ◽  
pp. 83-93
Author(s):  
Vikram Singh ◽  
Sandeep Kumar Arya ◽  
Manoj Kumar
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Low Noise ◽  
Ultra Wideband ◽  
Common Source ◽  
Cmos Process ◽  
Second Stage ◽  
Input Matching ◽  
Noise Amplifier ◽  
Noise Canceling

AbstractA 3–12 GHz ultra-wideband (UWB) low noise amplifier (LNA) is proposed in this paper. The first stage common-gate (CG), common-source (CS) noise canceling approach is used to achieve low noise-figure (NF). CG configuration at the input stage provides wideband input-matching. The noise of CG transistor is cancelled by systematically added two parallel CS transistors, whose outputs are cascoded in second stage. In order to achieve flat power gain (S21) response, a series peaking inductor is used in the second stage. The proposed LNA is designed in 90 nm CMOS process with chip-layout area of 0.467 mm2 and in comparison to the existing LNAs, it consumes a low power of 5.7 mW from a 1 V supply. The achieved input-reflection coefficient (S11) is <−7.5 dB, output-reflection coefficient (S22) is <−7.6 dB with NF < 5.8 dB for 3–12 GHz UWB and third-order intercept point (IIP3) of −19 dBm. It achieves high and flat S21 of 20.84 ± 0.28 dB over 4.2–10 GHz, with NF ranging from 2.6–3.6 dB.

PERFORMANCE ANALYSIS OF INDUCTIVELY DEGENERATED CMOS LNA

2016 ◽  
Vol 78 (6-3) ◽  
Author(s):  
Maizan Muhamad ◽  
Norhayati Soin ◽  
Harikrishnan Ramiah ◽  
Norlaili Mohd Noh
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Low Noise ◽  
Peak Performance ◽  
Efficient Design ◽  
Power Efficient ◽  
Gain Enhancement ◽  
Input Matching ◽  
Fixed Power ◽  
Noise Amplifier

This paper features the design approach of a low noise amplifier (LNA) which dissipates 19.89 mW from a 1.2 V power supply that was designed based on a 0.13 μm RFCMOS process. A detailed methodology that leads to a power-efficient design of the LNA is presented. A theoretical noise figure optimization using fixed power and physics-based gm/ID characteristics were used as a design optimization guide. Simultaneous noise and input matching under constrained power (PCSNIM) was achieved with an extra gate-source capacitor while gain enhancement was obtained by employing a capacitive feedback at the cascode transistor.  The LNA is further optimized by implementing the forward biasing scheme to attain good LNA performance at low power. The end-design of the optimized LNA produces a noise figure of 3.55 dB, a power gain of 17.12 dB, a Third Order Input Intercept Point (IIP3) of -19.70 dBm, an input reflection coefficient of -14.15 dB and an output reflection coefficient of -18.37 dB. Simulated results validate peak performance at 2.45GHz, which makes the LNA suitable for Bluetooth and the industrial, scientific and medical (ISM) applications.

Design of 3.1-10.6GHz CMOS LNA Based on Input Matching Technique of Common-Gate Topology

2013 ◽  
Vol 479-480 ◽  
pp. 1014-1017
Author(s):  
Yi Cheng Chang ◽  
Meng Ting Hsu ◽  
Yu Chang Hsieh
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Average Power ◽  
Wide Band ◽  
Low Noise ◽  
Input Matching ◽  
Common Gate ◽  
Cmos Lna ◽  
Noise Amplifier ◽  
Is Design

In this study, three stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. The UWB LNA is design in 0.18μm TSMC CMOS technique. The LNA input and output return loss are both less than-10dB, and achieved 10dB of average power gain, the minimum noise figure is 6.55dB, IIP3 is about-9.5dBm. It consumes 11mW from a 1.0-V supply voltage.

Design of a Ku-band MMIC LNA with a Simple T-type Input Matching Network

2020 ◽  
Vol 29 (11) ◽  
pp. 2020006
Author(s):  
Tian Qi ◽  
Songbai He ◽  
Cheng Zhong ◽  
Zhitao Zhu
Keyword(s):  
Integrated Circuit ◽  
Return Loss ◽  
Noise Figure ◽  
Low Noise ◽  
Matching Network ◽  
Monolithic Microwave Integrated Circuit ◽  
Input Matching ◽  
Satellite Applications ◽  
Feedback Structure ◽  
Noise Amplifier

In this paper, the design of a wideband monolithic microwave integrated circuit (MMIC) low-noise amplifier (LNA) fabricated in 0.13-[Formula: see text]m GaAs pHEMT process is presented. A simple T-type input matching network (IMN) and a source feedback structure are employed to achieve low noise figure (NF). The MMIC LNA, which operates across 12–18[Formula: see text]GHz, can be used for satellite applications. Experimental results show an NF around 1.5[Formula: see text]dB in 12–17.5[Formula: see text]GHz and a minimum NF of 1.21[Formula: see text]dB at 16.5[Formula: see text]GHz. In addition, a flat small-signal gain of [Formula: see text][Formula: see text]dB is achieved at 13.5–17.5[Formula: see text]GHz. The input return loss is lower than [Formula: see text] dB at 12–14.5[Formula: see text]GHz and the output return loss is lower than [Formula: see text] dB at 12–17[Formula: see text]GHz. The power consumed is lower than 0.3[Formula: see text]W and the [Formula: see text] (1-dB compression point) output power is around 13[Formula: see text]dBm.

Design of Low-Noise Two-Path Amplifier for 6–16 GHz Applications

2020 ◽  
pp. 2150136
Author(s):  
Asieh Parhizkar Tarighat ◽  
Mostafa Yargholi
Keyword(s):  
Noise Figure ◽  
Impedance Matching ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Input Matching ◽  
Inductive Peaking ◽  
Linearity Improvement ◽  
Noise Amplifier ◽  
Path Structure

A two-path low-noise amplifier (LNA) is designed with TSMC 0.18[Formula: see text][Formula: see text]m standard RF CMOS process for 6–16[Formula: see text]GHz frequency band applications. The principle of a conventional resistive shunt feedback LNA is analyzed to demonstrate the trade-off between the noise figure (NF) and the input matching. To alleviate the mentioned issue for wideband application, this structure with noise canceling technique and linearity improvement are applied to a two-path structure. Flat and high gain is supplied by the primary path; while the input and output impedance matching are provided by the secondary path. The [Formula: see text][Formula: see text]dB bandwidth can be increased to a higher frequency by inductive peaking, which is used at the first stage of the two paths. Besides, by biasing the transistors at the threshold voltage, low power dissipation is achieved. The [Formula: see text][Formula: see text]dB gain bandwidth of the proposed LNA is 10[Formula: see text]GHz, while the maximum power gain of 13.1[Formula: see text]dB is attained. With this structure, minimum NF of 4.6[Formula: see text]dB and noise flatness of 1[Formula: see text]dB in the whole bandwidth can be achieved. The input impedance is matched, and S[Formula: see text] is lower than [Formula: see text]10 dB. With the proposed linearized LNA, the average IIP[Formula: see text][Formula: see text]dBm is gained, while it occupies 1051.7[Formula: see text][Formula: see text]m die area.

A 6.5-kV HBM ESD-protected high-gain LNA using cascaded L-match input network

2019 ◽  
Vol 33 (23) ◽  
pp. 1950280
Author(s):  
Guoxiao Cheng ◽  
Zhiqun Li ◽  
Pengfei Yue ◽  
Lei Luo ◽  
Xiaodong He ◽  
...  
Keyword(s):  
Noise Figure ◽  
Nonlinear Coefficient ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Third Order ◽  
Input Matching ◽  
Third Stage ◽  
Protection Circuits ◽  
Noise Amplifier

A wideband (2–3 GHz) three-stage low noise amplifier (LNA) with electrostatic discharge (ESD) protection circuits using 0.18 [Formula: see text]m CMOS technology is presented in this paper. Low-parasitic silicon-controlled rectifier (SCR) devices are co-designed with the LNA in the form of [Formula: see text]-parameters, and a new cascaded L-match input network is proposed to reduce the parasitic effects of them on the input matching. To improve linearity performance, an optimized multiple-gated transistors method (MGTR) is proposed and applied to the third stage, which takes both transconductance [Formula: see text] and third-order nonlinear coefficient [Formula: see text] into consideration. The measured results show a wide input matching across 2–8 GHz and a high third-order input intercept point (IIP3) of −12.8 dBm. The peak power gain can achieve 29.1 dB, and the noise figure (NF) is in a range of 3.1–3.6 dB within the 3-dB bandwidth. Using SCR devices with low parasitic capacitance of [Formula: see text]80 fF and robust gate-driven power clamps, a 6.5-kV human body mode (HBM) ESD performance is obtained.

The Design and Modeling of 30 GHz Microwave Front-End

2012 ◽  
pp. 205-238
Author(s):  
Wan Yeen Ng ◽  
Xhiang Rhung Ng
Keyword(s):  
Millimeter Wave ◽  
Integrated Circuit ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Operating Frequency ◽  
Total Power ◽  
Automotive Radar ◽  
Gain Compression ◽  
Noise Amplifier

This chapter aims to discuss a millimeter wave integrated circuit (MMWIC) in frequency of 30 GHz especially switch (SPDT), medium power amplifier (MPA) and low noise amplifier (LNA). The switch is developed using a commercial 0.15 µm GaAs pHEMT technology. It achieves low loss and high isolation for millimeter wave applications. The circuit and layout drawing of SPDT switch are done by using Advanced Design System (ADS) software. The layout is verified by running the Design Rules Check (DRC) to check and clear all the errors. At the operating frequency of 30 GHz, the reported SPDT switch has 1.470 dB insertion loss and 37.455 dB of isolation. It also demonstrates 26.00 dBm of input P1dB gain compression point (P1dB) and 22.975 dBm of output P1dB. At a supply voltage of 3.0 V and 30 GHz operating frequency, this two-stage LNA achieves an associated gain of 21.628 dB, noise figure (NF) of 2.509 dB and output referred 1-dB compression point (P1dB) of -11.0 dBm, the total power consumptions for the LNA is 174 mW. At a supply voltage of 6.0 V and 30 GHz operating frequency, a 2-stage MPA achieves a linear gain (S21) of 13.236 dB, P1dB of 22.5 dBm, power gain of 11.055 dB and the PAE of 14.606%. The total power consumption for the MPA is 1.122 W. The 30 GHz LNA and PA can be applied in direct broadcast satellite (DBS), automotive radar transmitter and receiver.

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