scholarly journals Ultrahigh Frequency Ultrasonic Transducers Design with Low Noise Amplifier Integrated Circuit

Micromachines ◽  
2018 ◽  
Vol 9 (10) ◽  
pp. 515 ◽  
Author(s):  
Di Li ◽  
Chunlong Fei ◽  
Qidong Zhang ◽  
Yani Li ◽  
Yintang Yang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultrasonic Transducers ◽  
Oxide Semiconductor ◽  
Ultrahigh Frequency ◽  
Common Source ◽  
Echo Signal ◽  
Silicon Lens ◽  
Noise Amplifier

This paper describes the design of an ultrahigh frequency ultrasound system combined with tightly focused 500 MHz ultrasonic transducers and high frequency wideband low noise amplifier (LNA) integrated circuit (IC) model design. The ultrasonic transducers are designed using Aluminum nitride (AlN) piezoelectric thin film as the piezoelectric element and using silicon lens for focusing. The fabrication and characterization of silicon lens was presented in detail. Finite element simulation was used for transducer design and evaluation. A custom designed LNA circuit is presented for amplifying the ultrasound echo signal with low noise. A Common-source and Common-gate (CS-CG) combination structure with active feedback is adopted for the LNA design so that high gain and wideband performances can be achieved simultaneously. Noise and distortion cancelation mechanisms are also employed in this work to improve the noise figure (NF) and linearity. Designed by using a 0.35 μm complementary metal oxide semiconductor (CMOS) technology, the simulated power gain of the echo signal wideband amplifier is 22.5 dB at 500 MHz with a capacitance load of 1.0 pF. The simulated NF at 500 MHz is 3.62 dB.

scholarly journals Linearity improvement of differential CMOS low noise amplifier

2019 ◽  
Vol 14 (1) ◽  
pp. 407
Author(s):  
Maizan Muhamad ◽  
Norhayati Soin ◽  
Harikrishnan Ramiah
Keyword(s):  
Integrated Circuit ◽  
Wireless Lan ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Linearity Improvement ◽  
Noise Amplifier

<p>This paper presents the linearity improvement of differential CMOS low noise amplifier integrated circuit using 0.13um CMOS technology. In this study, inductively degenerated common source topology is adopted for wireless LAN application. The linearity of the single-ended LNA was improved by using differential structures with optimum biasing technique. This technique achieved better LNA and linearity performance compare with single-ended structure. Simulation was made by using the cadence spectre RF tool. Consuming 5.8mA current at 1.2V supply voltage, the designed LNA exhibits S<sub>21</sub> gain of 18.56 dB, noise figure (NF) of 1.85 dB, S<sub>11</sub> of −27.63 dB, S<sub>22</sub> of -34.33 dB, S<sub>12</sub> of −37.09 dB and IIP3 of -7.79 dBm.</p>

A Study on Scalability and Variation of CMOS Low Noise Amplifier in Advance CMOS Technology Processes

2016 ◽  
Vol 833 ◽  
pp. 135-139
Author(s):  
Dayang Nur Salmi Dharmiza Awang Salleh ◽  
Rohana Sapawi
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Rf Circuits ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Technology Scaling ◽  
Wireless Applications ◽  
Noise Amplifier ◽  
Technology Processes

Recent technology requires multistandard Radio Frequency (RF) chips for multipurpose wireless applications. In RF circuits, a low-noise amplifier (LNA) plays the key role in determining the receiver’s performance. With CMOS technology scaling, various designs has been adopted to study circuit’s characteristic and variation. In this paper, we present the results of scalable wideband LNA design based on complementary metal oxide semiconductor (CMOS), with its variance study. The design was fabricated in 180nm, 90nm, 65nm and 40nm CMOS technology.

An Inverter-Based Wideband Low-Noise Amplifier in 40 nm Complementary Metal Oxide Semiconductor

2012 ◽  
Vol 51 ◽  
pp. 04DE07 ◽  
Author(s):  
Dayang Nur Salmi Dharmiza ◽  
Mototada Oturu ◽  
Satoru Tanoi ◽  
Hiroyuki Ito ◽  
Noboru Ishihara ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Noise ◽  
Metal Oxide Semiconductor ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Noise Amplifier

scholarly journals Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology

2018 ◽  
Vol 7 (3) ◽  
pp. 143
Author(s):  
T. Kanthi ◽  
D. Sharath Babu Rao
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Power Gain ◽  
Amplifier Circuit ◽  
Folded Cascode ◽  
Noise Amplifier ◽  
5 Ghz

This paper is about Low noise amplifier topologies based on 0.18µm CMOS technology. A common source stage with inductive degeneration, cascode stage and folded cascode stage is designed, simulated and the performance has been analyzed. The LNA’s are designed in 5GHz. The LNA of cascode stage of noise figure (NF) 2.044dB and power gain 4.347 is achieved. The simulations are done in cadence virtuoso spectre RF.

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