scholarly journals Back-Channel Etched In-Ga-Zn-O Thin-Film Transistor Utilizing Selective Wet-Etching of Copper Source and Drain

Processes ◽  
2021 ◽  
Vol 9 (12) ◽  
pp. 2193
Author(s):  
Rauf Khan ◽  
Muhamad Affiq Bin Misran ◽  
Michitaka Ohtaki ◽  
Jun Tae Song ◽  
Tatsumi Ishihara ◽  
...  
Keyword(s):  
Thin Film ◽  
Electrical Properties ◽  
Active Layer ◽  
Threshold Voltage ◽  
Thin Film Transistor ◽  
Wet Etching ◽  
Electrical Performance ◽  
Indium Gallium Zinc Oxide ◽  
Saturation Region ◽  
Photolithography Process

The electrical performance of the back-channel etched Indium–Gallium–Zinc–Oxide (IGZO) thin-film transistors (TFTs) with copper (Cu) source and drain (S/D) which are patterned by a selective etchant was investigated. The Cu S/D were fabricated on a molybdenum (Mo) layer to prevent the Cu diffusion to the active layer (IGZO). We deposited the Cu layer using thermal evaporation and performed the selective wet etching of Cu using a non-acidic special etchant without damaging the IGZO active layer. We fabricated the IGZO TFTs and compared the performance in terms of linear and saturation region mobility, threshold voltage and ON current (ION). The IGZO TFTs with Mo/Cu S/D exhibit good electrical properties, as the linear region mobility is 12.3 cm2/V-s, saturation region mobility is 11 cm2/V-s, threshold voltage is 1.2 V and ION is 3.16 × 10−6 A. We patterned all the layers by a photolithography process. Finally, we introduced a SiO2-ESL layer to protect the device from external influence. The results show that the prevention of Cu and the introduced ESL layer enhances the electrical properties of IGZO TFTs.

scholarly journals Back-channel Etched In-Ga-Zn-O Thin-film Transistor Utilizing Selective Wet-Etching of Copper Source and Drain

2021 ◽  
Author(s):  
Rauf Khan ◽  
Muhamad Affiq Bin Misran ◽  
Reiji Hattori
Keyword(s):  
Thin Film ◽  
Electrical Properties ◽  
Active Layer ◽  
Threshold Voltage ◽  
Thermal Evaporation ◽  
Thin Film Transistor ◽  
Wet Etching ◽  
Electrical Performance ◽  
Saturation Region ◽  
Photolithography Process

The electrical performance of the back-channel etched Indium–Gallium–Zinc–Oxide (IGZO) thin-film transistors (TFTs) with copper (Cu) source and drain (S/D) which are patterned by a selective etchant was investigated. The Cu S/D were fabricated on molybdenum (Mo) layer to prevent the Cu diffusion to the active layer (IGZO). We deposited the Cu layer using thermal evaporation and performed the selective wet etching of Cu using non-acidic special etchant without damaging the IGZO active layer. We fabricated the IGZO TFTs and compare the performance in terms of linear and saturation region mobility, threshold voltage and ON current (ION). The IGZO TFTs with Mo/Cu S/D exhibits good electrical properties as the linear region mobility is 12.3 cm2/V-s, saturation region mobility is 11 cm2/V-s, threshold voltage is 1.2 V and ION is 3.16 x 10-6 A. We patterned all the layers by photolithography process. Finally, we introduced SiO2-ESL layer to protect the device from the external influence. The results show that the prevention of Cu and introduced ESL layer enhances the electrical properties of IGZO TFTs.

scholarly journals Investigation of the Electrical Properties of Double-Gate Dual-Active-Layer (DG-DAL) Thin-Film Transistor (TFT) with HfO-=SUB=-2-=/SUB=-/La-=SUB=-2-=/SUB=-O-=SUB=-3-=/SUB=-/HfO-=SUB=-2-=/SUB=- (HLH) Sandwich Gate Dielectrics

2020 ◽  
Vol 54 (10) ◽  
pp. 1098
Author(s):  
L. Ramesh ◽  
S. Moparthi ◽  
P.K. Tiwari ◽  
V.R. Samoju ◽  
G.K. Saramekala
Keyword(s):  
Thin Film ◽  
Electrical Properties ◽  
Active Layer ◽  
Threshold Voltage ◽  
Thin Film Transistor ◽  
Hafnium Dioxide ◽  
Subthreshold Swing ◽  
Oxide Material ◽  
Double Gate ◽  
Pixel Intensity

In this paper, the electrical properties of a double-gate dual-active-layer (DG-DAL) thin-film transistor (TFT) is investigated. To increase the ON-current and pixel intensity, and control the voltage stress bias, the conventional gate oxide material (silicon dioxide SiO2) is replaced with a tri-high-k gate dielectric layer, hafnium dioxide HfO2/lanthanum oxide La2O3/hafnium dioxide HfO2 (HLH). Further, the performance of the proposed DG-DAL structure is compared with the single-active-layer (SAL) and dual-active-layer (DAL) TFTs. The amorphous indium-gallium zinc-oxide (a-IGZO) is considered as active layer for SAL channel region, and on the other hand, a-IGZO and indium-tin-oxide (ITO) are considered as active layers for DAL TFT and DG-DAL TFT channel regions. The parameters such as OFF-current, ON-current, ION/IOFF ratio, threshold voltage, mobility, average subthreshold swing, etc. are evaluated for the considered structures. It is observed that the DG-DAL TFT with HLH dielectric offers high ON-current of 3.85·10-3 A/μm, very low OFF-current of 2.53·10-17 A/μm, very high ION/IOFF ratio of 1.51·1014, the threshold voltage of 0.642 V, high mobility of 35 cm2·v-1·s-1 and average subthreshold swing of 127.84 mV/dec. A commercial TCAD simulation tool ATLAS from SilvacoTM is used to investigate all the parameters for considered structures. Keywords: single active layer (SAL), dual active layer (DAL), double-gate dual active layer (DG-DAL), InGaZnO (IGZO), InSnO (ITO), thin-film transistor (TFT), HfO2/La2O3/HfO2 (HLH).

scholarly journals A Study on Solution-Processed Y2O3 Films Modified by Atomic Layer Deposition Al2O3 as Dielectrics in ZnO Thin Film Transistor

Coatings ◽  
2021 ◽  
Vol 11 (8) ◽  
pp. 969
Author(s):  
Haiyang Xu ◽  
Xingwei Ding ◽  
Jie Qi ◽  
Xuyong Yang ◽  
Jianhua Zhang
Keyword(s):  
Thin Film ◽  
Atomic Layer Deposition ◽  
Active Layer ◽  
Dielectric Layer ◽  
Thin Film Transistor ◽  
Atomic Layer ◽  
Electrical Performance ◽  
Zno Thin Film ◽  
Threshold Voltage Shift ◽  
Layer Deposition

In this work, Y2O3–Al2O3 dielectrics were prepared and used in ZnO thin film transistor as gate insulators. The Y2O3 film prepared by the sol–gel method has many surface defects, resulting in a high density of interface states with the active layer in TFT, which then leads to poor stability of the devices. We modified it by atomic layer deposition (ALD) technology that deposited a thin Al2O3 film on the surface of a Y2O3 dielectric layer, and finally fabricated a TFT device with ZnO as the active layer by ALD. The electrical performance and bias stability of the ZnO TFT with a Y2O3–Al2O3 laminated dielectric layer were greatly improved, the subthreshold swing was reduced from 147 to 88 mV/decade, the on/off-state current ratio was increased from 4.24 × 106 to 4.16 × 108, and the threshold voltage shift was reduced from 1.4 to 0.7 V after a 5-V gate was is applied for 800 s.

Numerical Design of Carrier Transporting Layer in Top-Gate InGaZnO Thin-Film Transistors for Controlling Potential Energy

2021 ◽  
Vol 21 (7) ◽  
pp. 3847-3852
Author(s):  
Do-Kyung Kim ◽  
Jihwan Park ◽  
Premkumar Vincent ◽  
Jun-Ik Park ◽  
Jaewon Jang ◽  
...  
Keyword(s):  
Thin Film ◽  
Potential Energy ◽  
Threshold Voltage ◽  
Structural Design ◽  
Thin Film Transistors ◽  
High Mobility ◽  
Electrical Performance ◽  
Indium Gallium Zinc Oxide ◽  
Semiconductor Interfaces ◽  
Efficient Charge

Top-gate amorphous indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) are designed with numerical analysis to control their electron potential energy. Design simulations show the effects of structural design on the electrical characteristics of these TFTs. In particular, the thicknesses of the channel (tch) and conducting (tc) layers, which play vital roles in TFT electrical performance, are varied from 1 to 50 nm to investigate the effect of thicknesses on the electron potential energies of the channel region and the electrode-semiconductor interfaces. The potential energies are precisely optimized for efficient charge transport, injection, and extraction, thus enhancing the electrical performance of these devices. It is also demonstrated that tch mainly affects mobility and threshold voltage, while tc mainly affects on-current. An acceptable threshold voltage of 0.55 V and high mobility of 14.7 cm2V−1s−1 are obtained with a tch of 30 nm and tc of 10 nm. Controllability of the electron potential energies and electrical performance of IGZO TFTs by means of structural design will contribute to realization of next-generation displays that have large areas and high resolutions.

Electrical Properties of Si-doped ZnO-based Thin-film Transistor with Dual-active-layer Structure

2015 ◽  
Vol 36 (2) ◽  
pp. 213-218
Author(s):  
莫淑芬 MO Shu-fen ◽  
刘玉荣 LIU Yu-rong ◽  
刘远 LIU Yuan
Keyword(s):  
Thin Film ◽  
Electrical Properties ◽  
Active Layer ◽  
Layer Structure ◽  
Thin Film Transistor ◽  
Si Doped ◽  
Doped Zno

Electrical Properties of Solution Processed In–Ga–ZnO Thin Film Transistors with Multi-Stacked Active Layer

2015 ◽  
Vol 15 (10) ◽  
pp. 7508-7512 ◽  
Author(s):  
Soon Kon Kim ◽  
Pyung Ho Choi ◽  
Sang Sub Kim ◽  
Hyun Woo Kim ◽  
Na Young Lee ◽  
...  
Keyword(s):  
Thin Film ◽  
Electrical Properties ◽  
Active Layer ◽  
Thin Film Transistors ◽  
High Mobility ◽  
Electrical Performance ◽  
Zno Thin Film ◽  
Threshold Voltage Shift ◽  
Active Layers ◽  
Current Path

In this study, we prepared solution-based In–Ga–ZnO thin film transistors (IGZO TFTs) having a multistacked active layer. The solution was prepared using an In:Zn = 1:1 mole ratio with variation in Ga content, and the TFTs were fabricated by stacking layers from the prepared solutions. After we measured the mobility of each stacked layer, the saturation mobility showed values of 0.8, 0.6 and 0.4 (cm2/Vs), with an overall decrease in electrical properties. The interface formed between the each layers affected the current path, resulting in reduced electrical performance. However, when the gate bias VG = 10 V was applied for 1500 s, the threshold voltage shift decreased in the stack. The uniformity of the active layer was improved in the stacked active layer by filling the hole formed during pre-baking, resulting in improved device stability. Also, the indium ratio was increased to enhance the mobility from 0.86 to 3.47. These results suggest high mobility and high stability devices can be produced with multistacked active layers.

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