scholarly journals Portable Immunosensor Based on Extended Gate—Field Effect Transistor for Rapid, Sensitive Detection of Cancer Markers

Proceedings ◽  
2019 ◽  
Vol 15 (1) ◽  
pp. 32
Author(s):  
Baldacchini ◽  
Bizzarri ◽  
Montanarella ◽  
Pascali ◽  
Lorenzelli ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Drain Current ◽  
Oxide Semiconductor ◽  
Sensitive Detection ◽  
High Current ◽  
Sensor Device ◽  
Current Variation ◽  
Gate Potential ◽  
Effect Transistor

We present an immunosensor for the rapid and sensitive detection of the p53 oncosuppressor protein and of its mutated form p53R175H, which are both valuable cancer biomarkers. The sensor is based on the accurate measurement of the source-drain current variation of a metal oxide semiconductor field-effect transistor, as due to the gate potential changing arising from charge release upon the selective capture of a biomarker by the partner immobilized on a sensing surface connected to the gate electrode. A suitable microelectronic system is implemented to combine high current resolution, which is needed to be competitive with standard immunoassays, with compact dimensions of the final sensor device.

Quantum Modelling of Nanoscale Silicon Gate-All-Around Field Effect Transistor

2020 ◽  
Vol 64 ◽  
pp. 115-122
Author(s):  
P. Vimala ◽  
N.R. Nithin Kumar
Keyword(s):  
Analytical Model ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Inversion Layer ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Effect Transistor ◽  
Quantum Mechanical Effects ◽  
Novel Devices

The paper introduces an analytical model for gate all around (GAA) or Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (SG-MOSFET) inclusive of quantum mechanical effects. The classical oxide capacitance is replaced by the capacitance incorporating quantum effects by including the centroid parameter. The quantum variant of inversion charge distribution function, inversion layer capacitance, drain current, and transconductance expressions are modeled by employing this model. The established analytical model results agree with the simulated results, verifying these models' validity and providing theoretical supports for designing and applying these novel devices.

scholarly journals Subthreshold Characteristics of a Metal-Oxide–Semiconductor Field-Effect Transistor with External PVDF Gate Capacitance

Crystals ◽  
2019 ◽  
Vol 9 (12) ◽  
pp. 673
Author(s):  
Jing-Jenn Lin ◽  
Ji-Hua Tao ◽  
You-Lin Wu
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Subthreshold Slope ◽  
Ferroelectric Capacitor ◽  
In Series ◽  
Effect Transistor

An organic ferroelectric capacitor, using polyvinylidene difluoride (PVDF) as the dielectric, was fabricated. By connecting the PVDF capacitor in series to the gate of a commercially purchased metal-oxide–semiconductor field-effect transistor (MOSFET), drain current (ID)–drain voltage (VD) characteristics and drain current (ID)–gate voltage (VG) characteristics were measured. In addition, the subthreshold slopes of the MOSFET were determined from the ID–VG curves. It was found that the subthreshold slope could be effectively reduced by 23% of its original value when the PVDF capacitor was added to the gate of the MOSFET.

An Extensive Simulation Study of Gate Underlap Influence on Device Performance of Surrounding Gate In0.53Ga0.47As/InP Hetero Field Effect Transistor

2020 ◽  
Vol 10 (2) ◽  
pp. 157-165
Author(s):  
Soumya S. Mohanty ◽  
Urmila Bhanja ◽  
Guru P. Mishra
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Model Simulation ◽  
Drain Current ◽  
Oxide Semiconductor ◽  
Device Performance ◽  
Short Channel ◽  
Effect Transistor ◽  
Rf Performance ◽  
Gate Underlap

Background: This work describes the implementation of In0.53Ga0.47As/InP Surrounding Metal Gate Oxide Semiconductor Heterostructure Field Effect Transistor (SG MOSHFET) with gate underlap on both source and drain end to improve the DC and RF performance. Methods: A comprehensive and methodological investigation of DC and RF performance of III-V semiconductor are made for different underlap length varying from 5nm to 30nm on both sides of the device, which is used to mitigate the short channel issues to improve the device performance. Hydrodynamic model has been taken into consideration for the device simulation and it also includes Auger recombination and the Shockley–Read–Hall (SRH) model. Simulation is performed to analyze the various analog performance of device like drain current, surface potential, transconductance, threshold voltage, drain induced barrier lowering, off current, subthreshold slope, Ion/Ioff ratio, output conductance, intrinsic delay, energy-delay product, transconductance generation factor and radio frequency performance of device, like trans-frequency product and cut-off frequency. Results: From the simulation, it can be observed that an improved analog and RF performance is obtained at the optimum underlap length. Conclusion: This work delivers an idea for extended researchers to investigate different aspects of group III–V underlap MOSFETs.

scholarly journals Improving the Performance of the ToGoFET Probe: Advances in Design, Fabrication, and Signal Processing

Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1303
Author(s):  
Hoontaek Lee ◽  
Junsoo Kim ◽  
Kumjae Shin ◽  
Wonkyu Moon
Keyword(s):  
Signal Processing ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Complementary Metal Oxide Semiconductor ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Effect Transistor

We report recent improvements of the tip-on-gate of field-effect-transistor (ToGoFET) probe used for capacitive measurement. Probe structure, fabrication, and signal processing were modified. The inbuilt metal-oxide-semiconductor field-effect-transistor (MOSFET) was redesigned to ensure reliable probe operation. Fabrication was based on the standard complementary metal-oxide-semiconductor (CMOS) process, and trench formation and the channel definition were modified. Demodulation of the amplitude-modulated drain current was varied, enhancing the signal-to-noise ratio. The - characteristics of the inbuilt MOSFET reflect the design and fabrication modifications, and measurement of a buried electrode revealed improved ToGoFET imaging performance. The minimum measurable value was enhanced 20-fold.

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