scholarly journals Miniaturized 0.13-μm CMOS Front-End Analog for AlN PMUT Arrays

Sensors ◽  
2020 ◽  
Vol 20 (4) ◽  
pp. 1205 ◽  
Author(s):  
Iván Zamora ◽  
Eyglis Ledesma ◽  
Arantxa Uranga ◽  
Núria Barniol
Keyword(s):  
Integrated Circuit ◽  
Imaging System ◽  
Ultrasonic Transducer ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Axial Distance ◽  
Cmos Integrated Circuit ◽  
Front End ◽  
Analog Front End

This paper presents an analog front-end transceiver for an ultrasound imaging system based on a high-voltage (HV) transmitter, a low-noise front-end amplifier (RX), and a complementary-metal-oxide-semiconductor, aluminum nitride, piezoelectric micromachined ultrasonic transducer (CMOS-AlN-PMUT). The system was designed using the 0.13-μm Silterra CMOS process and the MEMS-on-CMOS platform, which allowed for the implementation of an AlN PMUT on top of the CMOS-integrated circuit. The HV transmitter drives a column of six 80-μm-square PMUTs excited with 32 V in order to generate enough acoustic pressure at a 2.1-mm axial distance. On the reception side, another six 80-μm-square PMUT columns convert the received echo into an electric charge that is amplified by the receiver front-end amplifier. A comparative analysis between a voltage front-end amplifier (VA) based on capacitive integration and a charge-sensitive front-end amplifier (CSA) is presented. Electrical and acoustic experiments successfully demonstrated the functionality of the designed low-power analog front-end circuitry, which outperformed a state-of-the art front-end application-specific integrated circuit (ASIC) in terms of power consumption, noise performance, and area.

A Charge Amplifier Based Complementary Metal–Oxide–Semiconductor Analog Front End for Piezoelectric Microphones in Hearing Aid Devices

2019 ◽  
Vol 15 (3) ◽  
pp. 315-322
Author(s):  
Manu Chilukuri ◽  
Sungyong Jung ◽  
Hoon-Ju Chung
Keyword(s):  
Hearing Aid ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Charge Amplifier ◽  
Front End ◽  
Analog Front End ◽  
A Charge ◽  
Cascode Current Mirror

In this paper, a low noise and low power analog front end for piezoelectric microphones used in hearing aid devices is presented. It consists of a Charge Amplifier, followed by a Variable Gain Amplifier and an Analog-to-Digital Converter. At the core of charge amplifier a two stage opamp with modified cascode current mirror is designed which achieves a gain of 93 dB and phase margin of 62°. Designed analog front end achieves an input referred noise of 0.12 μVrms and SNR of 74 dB. It consumes power of 430 μW from 1.8 V supply and occupies an area of 1.2 mm × 0.22 mm. Proposed circuit is designed and fabricated in 0.18 μm CMOS process. Designed circuit is interfaced with a sensor model of piezoelectric microphone, which mimics Ormia ochracea's auditory system, and its performance is successfully verified against simulation results.

scholarly journals 14.85 µW Analog Front-End for Photoplethysmography Acquisition with 142-dBΩ Gain and 64.2-pArms Noise

Sensors ◽  
2019 ◽  
Vol 19 (3) ◽  
pp. 512
Author(s):  
Binghui Lin ◽  
Mohamed Atef ◽  
Guoxing Wang
Keyword(s):  
Dynamic Range ◽  
Automatic Gain Control ◽  
Gain Control ◽  
Low Noise ◽  
Total Power ◽  
Cmos Process ◽  
Control Block ◽  
Silicon Area ◽  
Front End ◽  
Analog Front End

A low-power, high-gain, and low-noise analog front-end (AFE) for wearable photoplethysmography (PPG) acquisition systems is designed and fabricated in a 0.35 μm CMOS process. A high transimpedance gain of 142 dBΩ and a low input-referred noise of only 64.2 pArms was achieved. A Sub-Hz filter was integrated using a pseudo resistor, resulting in a small silicon area. To mitigate the saturation problem caused by background light (BGL), a BGL cancellation loop and a new simple automatic gain control block are used to enhance the dynamic range and improve the linearity of the AFE. The measurement results show that a DC photocurrent component up-to-10 μA can be rejected and the PPG output swing can reach 1.42 Vpp at THD < 1%. The chip consumes a total power of 14.85 μW using a single 3.3-V power supply. In this work, the small area and efficiently integrated blocks were used to implement the PPG AFE and the silicon area is minimized to 0.8 mm × 0.8 mm.

scholarly journals A 0.5 V 68 nW ECG Monitoring Analog Front-End for Arrhythmia Diagnosis

2018 ◽  
Vol 8 (3) ◽  
pp. 27 ◽  
Author(s):  
Avish Kosari ◽  
Jacob Breiholz ◽  
NingXi Liu ◽  
Benton Calhoun ◽  
David Wentzloff
Keyword(s):  
Low Power ◽  
Power Efficiency ◽  
Low Noise ◽  
Signal Acquisition ◽  
Cmos Process ◽  
Ecg Signal ◽  
Ecg Monitoring ◽  
Power Circuit ◽  
Front End ◽  
Analog Front End

This paper presents a power efficient analog front-end (AFE) for electrocardiogram (ECG) signal monitoring and arrhythmia diagnosis. The AFE uses low-noise and low-power circuit design methodologies and aggressive voltage scaling to satisfy both the low power consumption and low input-referred noise requirements of ECG signal acquisition systems. The AFE was realized with a three-stage fully differential AC-coupled amplifier, and it provides bio-signal acquisition with programmable gain and bandwidth. The AFE was implemented in a 130 nm CMOS process, and it has a measured tunable mid-band gain from 31 to 52 dB with tunable low-pass and high-pass corner frequencies. Under only 0.5 V supply voltage, it consumes 68 nW of power with an input-referred noise of 2.8 µVrms and a power efficiency factor (PEF) of 3.9, which makes it very suitable for energy-harvesting applications. The low-noise 68nW AFE was also integrated on a self-powered physiological monitoring System on Chip (SoC) that is used to capture ECG bio-signals. Heart rate extraction (R-R) detection algorithms were implemented and utilized to analyze the ECG data received by the AFE, showing the feasibility of <100 nW AFE for continuous ECG monitoring applications.

PD/sup 3/, a low-noise precise timing analog front-end integrated circuit

2002 ◽  
Author(s):  
R. Beccherle ◽  
M.G. Bisogni ◽  
A. Cisternino ◽  
A. Del Guerra ◽  
M. Folli ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Noise ◽  
Precise Timing ◽  
Front End ◽  
Analog Front End

scholarly journals An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1760
Author(s):  
Folla Kamdem Jérôme ◽  
Wembe Tafo Evariste ◽  
Essimbi Zobo Bernard ◽  
Maria Liz Crespo ◽  
Andres Cicuttin ◽  
...  
Keyword(s):  
Low Power ◽  
High Throughput ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
High Luminosity ◽  
Gain Bandwidth ◽  
Wide Bandwidth ◽  
Ultra Low Power ◽  
Front End

The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consumption and higher readout bandwidth to match the low power requirement of its Short Strip application-specific integrated circuits (ASIC) (SSA) and to handle a large number of pileup events in the High-Luminosity Large Hadron Collider (LHC). A low-noise, wide bandwidth, and ultra-low power FEE for the pixel-strip sensor of the CMS has been designed and simulated in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process. The design comprises a Charge Sensitive Amplifier (CSA) and a fast Capacitor-Resistor-Resistor-Capacitor (CR-RC) pulse shaper (PS). A compact structure of the CSA circuit has been analyzed and designed for high throughput purposes. Analytical calculations were performed to achieve at least 998 MHz gain bandwidth, and then overcome pileup issue in the High-Luminosity LHC. The spice simulations prove that the circuit can achieve 88 dB dc-gain while exhibiting up to 1 GHz gain-bandwidth product (GBP). The stability of the design was guaranteed with an 82-degree phase margin while 214 ns optimal shaping time was extracted for low-power purposes. The robustness of the design against radiations was performed and the amplitude resolution of the proposed front-end was controlled at 1.87% FWHM (full width half maximum). The circuit has been designed to handle up to 280 fC input charge pulses with 2 pF maximum sensor capacitance. In good agreement with the analytical calculations, simulations outcomes were validated by post-layout simulations results, which provided a baseline gain of 546.56 mV/MeV and 920.66 mV/MeV, respectively, for the CSA and the shaping module while the ENC (Equivalent Noise Charge) of the device was controlled at 37.6 e− at 0 pF with a noise slope of 16.32 e−/pF. Moreover, the proposed circuit dissipates very low power which is only 8.72 µW from a 3.3 V supply and the compact layout occupied just 0.0205 mm2 die area.

scholarly journals A High-Temperature, Low-Noise Readout ASIC for MEMS-Based Accelerometers

Sensors ◽  
2019 ◽  
Vol 20 (1) ◽  
pp. 241 ◽  
Author(s):  
Min Qi ◽  
An-qiang Guo ◽  
Dong-hai Qiao
Keyword(s):  
Integrated Circuit ◽  
Sampling Technique ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Frequency Noise ◽  
Voltage Reference ◽  
Noise Floor ◽  
Mems Sensor ◽  
Output Noise

This paper presents the development and measurement results of a complementary metal oxide semiconductor (CMOS) readout application-specific integrated circuit (ASIC) for bulk-silicon microelectromechanical system (MEMS) accelerometers. The proposed ASIC converts the capacitance difference of the MEMS sensor into an analog voltage signal and outputs the analog signal with a buffer. The ASIC includes a switched-capacitor analog front-end (AFE) circuit, a low-noise voltage reference generator, and a multi-phase clock generator. The correlated double sampling technique was used in the AFE circuits to minimize the low-frequency noise of the ASIC. A programmable capacitor array was implemented to compensate for the capacitance offset of the MEMS sensor. The ASIC was developed with a 0.18 μm CMOS process. The test results show that the output noise floor of the low-noise amplifier was −150 dBV/√Hz at 100 Hz and 175 °C, and the sensitivity of the AFE was 750 mV/pF at 175 °C. The output noise floor of the voltage reference at 175 °C was −133 dBV/√Hz at 10 Hz and −152 dBV/√Hz at 100 Hz.

Evaluation of Low-Noise Analog Front-End Application Specific Integrated Circuit for Solid-State Detectors

2008 ◽  
Vol 47 (5) ◽  
pp. 3423-3427 ◽  
Author(s):  
Tetsuichi Kishishita ◽  
Hirokazu Ikeda ◽  
Tatsuya Kiyuna ◽  
Hajimu Yasuda ◽  
Ken-ichi Tamura ◽  
...  
Keyword(s):  
Solid State ◽  
Integrated Circuit ◽  
Low Noise ◽  
Front End ◽  
Solid State Detectors ◽  
Analog Front End ◽  
Application Specific Integrated Circuit ◽  
Application Specific

scholarly journals CMOS Analog Front-End IC for Gas Sensors

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001761-001796
Author(s):  
Hyuntae Kim ◽  
Bertan Bakkaloglu
Keyword(s):  
Detection System ◽  
Sensor Arrays ◽  
Low Noise ◽  
Atmospheric Pollutants ◽  
Amperometric Sensor ◽  
Cmos Process ◽  
Current Steering ◽  
Front End ◽  
Analog Front End ◽  
Conductometric Sensor

An electrochemical sensor readout analog front-end (AFE) IC for recording long term chemical and gas exposure is presented. The AFE readout circuit enables the detection of exhaust fumes in hazardous diesel and gasoline equipment, which helps correlate atmospheric pollutants with severe illnesses. The AFE reads out the output of eight conductometric sensor arrays and eight amperometric sensor arrays. The IC consists of a low noise potentiostat and associated 9 bits current-steering DAC for sensor stimulus, followed by the first order nested chopped ΣΔ ADC. The conductometric sensor uses a current driven approach for extracting resistance change of the sensor depending on gas concentration. The amperometric sensor uses a potentiostat to apply constant voltage for measuring current out of the sensor after a chemical reaction. The core area for the AFE is 2.65x0.95 mm2. The IC is fabricated in 0.18μm CMOS process and achieves 91dB SNR with 1.32mW power consumption per channel from a 1.8 V supply. With digital offset storage and nested chopping, the readout IC achieves 500 μV input referred offset. In order to use the system with AFE as part of a compact badge with battery, the entire gas detection system has been designed in 3D layers with a bio sensor mounted layer, an AFE layer, power management layer, a micro controller layer, and battery.

A Highly-Integrated Low-Noise MICS Band Receiver RF Front-End IC with AC-Coupled Current Mirror Amplifier

2018 ◽  
Vol 28 (01) ◽  
pp. 1950010 ◽  
Author(s):  
Hyouk-Kyu Cha
Keyword(s):  
Integrated Circuit ◽  
Noise Figure ◽  
Low Noise ◽  
Cmos Process ◽  
Noise Current ◽  
Simulated Performance ◽  
Front End ◽  
Rf Front End ◽  
Mics Band ◽  
Layout Area

This work presents a low-noise, low-power receiver RF front-end integrated circuit (IC) for 402–405[Formula: see text]MHz medical implant communications service (MICS) band applications using 0.18-[Formula: see text]m CMOS process. The proposed front-end employs an AC-coupled current mirroring amplifier in between the low-noise current-reuse transconductor amplifier and a single-balanced IQ mixer for improved gain and noise performance in comparison to previous works. The designed front-end IC achieves a simulated performance of 36.5[Formula: see text]dB conversion gain, 1.85[Formula: see text]dB noise figure, and IIP3 of [Formula: see text][Formula: see text]dBm while consuming 440[Formula: see text][Formula: see text]W from 1-V voltage supply. The consumed core layout area, including I/Q LO generation and current bias circuits, is only 0.29[Formula: see text]mm2.

A Floating-Gate-Based Four-Channel Reconfigurable Analog Front-End Integrated Circuit

2021 ◽  
Author(s):  
Zu-Jia Lo ◽  
Bipasha Nath ◽  
Yuan-Chuan Wang ◽  
Yun-Jie Huang ◽  
Hui-Chun Huang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Floating Gate ◽  
Front End ◽  
Analog Front End
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