scholarly journals Enhanced Infrared Absorbance of the CMOS Compatible Thermopile by the Subwavelength Rectangular-Hole Arrays

Sensors ◽  
2020 ◽  
Vol 20 (11) ◽  
pp. 3218 ◽  
Author(s):  
Chi-Feng Chen ◽  
Chih-Hsiung Shen ◽  
Yun-Ying Yeh
Keyword(s):  
Fdtd Method ◽  
Complementary Metal Oxide Semiconductor ◽  
Absorption Efficiency ◽  
Oxide Semiconductor ◽  
Fdtd Simulation ◽  
Target Temperature ◽  
Rectangular Hole ◽  
Geometric Conditions ◽  
Cmos Compatible ◽  
Hole Arrays

The enhanced infrared absorbance (IRA) of the complementary metal-oxide-semiconductor (CMOS) compatible thermopile with the subwavelength rectangular-hole arrays in active area is investigated. The finite-difference time-domain (FDTD) method considered and analyzed the matrix arrangement (MA) and staggered arrangement (SA) of subwavelength rectangular-hole arrays (SRHA). For the better cases of MA-SRHA and SA-SRHA, the geometric parameters are the same and the infrared absorption efficiency (IAE) of the SA type is better than that of the MA type by about 19.4% at target temperature of 60 °C. Three proposed thermopiles with SA-SRHA are manufactured based on the 0.35 μm 2P4M CMOS-MEMS process. The measurement results are similar to the simulation results. The IAE of the best simulation case of SA-SRHA is up to 3.3 times higher than that without structure at the target temperature of 60 °C. Obviously, the staggered rectangular-hole arrays with more appropriate geometric conditions obtained from FDTD simulation can excellently enhance the IRA of the CMOS compatible thermopile.

scholarly journals A Thermopile Device with Subwavelength Structure by CMOS-MEMS Technology

2019 ◽  
Vol 9 (23) ◽  
pp. 5118 ◽  
Author(s):  
Chih-Hsiung Shen ◽  
Yun-Ying Yeh ◽  
Chi-Feng Chen
Keyword(s):  
Fdtd Method ◽  
Complementary Metal Oxide Semiconductor ◽  
Absorption Efficiency ◽  
Oxide Semiconductor ◽  
Visible Range ◽  
Subwavelength Structure ◽  
Mems Technology ◽  
Cmos Mems ◽  
Cmos Compatible ◽  
Simulation Results

Besides the application of the photonic crystal for the photodetector in the visible range, the infrared devices proposed with subwavelength structure are numerically and experimentally investigated thoroughly for infrared radiation sensing in this research. Several complementary metal oxide semiconductor (CMOS) compatible thermopiles with subwavelength structure (SWS) are proposed and simulated by the FDTD method. The proposed thermopiles are fabricated by the 0.35 μm 2P4M CMOS-MEMS process in TSMC (Taiwan Semiconductor Manufacturing Company). The measurement and simulation results show that the response of these devices with SWS is higher than for those without SWS. The trend of the measurement results is consistent with that of the simulation results. Obviously, the absorption efficiency of the CMOS compatible thermopile can be enhanced when the subwavelength structure exists.

scholarly journals Infrared Absorption Efficiency Enhancement of the CMOS Compatible Thermopile by the Special Subwavelength Hole Arrays

2020 ◽  
Vol 10 (8) ◽  
pp. 2966 ◽  
Author(s):  
Yun-Ying Yeh ◽  
Chih-Hsiung Shen ◽  
Chi-Feng Chen
Keyword(s):  
Infrared Absorption ◽  
Absorption Efficiency ◽  
Hole Array ◽  
Rectangular Hole ◽  
Efficiency Enhancement ◽  
Cmos Compatible ◽  
Subwavelength Hole Arrays ◽  
Hole Arrays ◽  
Difference Time ◽  
Rectangular Columns

The infrared absorption efficiency (IAE) enhancement of the complementary-metal-oxide-semiconductorCMOS compatible thermopile with special subwavelength hole arrays in an active area was numerically investigated by the finite-difference time-domain method. It was found that the absorption efficiency of that thermopile was enhanced when the subwavelength rectangular-hole array added extra rectangular-columnar or ellipse-columnar structures in the hole array. The simulation results show that the IAEs of the better cases for the three types of rectangular columns and three ellipse columns were increased by 14.4% and 15.2%, respectively. Such special subwavelength hole arrays can be improved by the IAE of the CMOS compatible thermopile.

scholarly journals A Thermopile Device with Sub-Wavelength Hole Arrays by CMOS-MEMS Technology

Sensors ◽  
2020 ◽  
Vol 21 (1) ◽  
pp. 180
Author(s):  
Chi-Feng Chen ◽  
Chih-Hsiung Shen ◽  
Yun-Ying Yeh
Keyword(s):  
Fdtd Method ◽  
Elliptical Hole ◽  
Oxide Semiconductor ◽  
Active Area ◽  
Hole Array ◽  
Cmos Mems ◽  
Simulation Results ◽  
Hole Arrays ◽  
Hole Structure ◽  
Sub Wavelength

A thermopile device with sub-wavelength hole array (SHA) is numerically and experimentally investigated. The infrared absorbance (IRA) effect of SHAs in active area of the thermopile device is clearly analyzed by the finite-difference time-domain (FDTD) method. The prototypes are manufactured by the 0.35 μm 2P4M complementary metal-oxide-semiconductor micro-electro-mechanical-systems (CMOS-MEMS) process in Taiwan semiconductor manufacturing company (TSMC). The measurement results of those prototypes are similar to their simulation results. Based on the simulation technology, more sub-wavelength hole structural effects for IRA of such thermopile device are discussed. It is found from simulation results that the results of SHAs arranged in a hexagonal shape are significantly better than the results of SHAs arranged in a square and the infrared absorption efficiencies (IAEs) of specific asymmetric rectangle and elliptical hole structure arrays are higher than the relatively symmetric square and circular hole structure arrays. The overall best results are respectively up to 3.532 and 3.573 times higher than that without sub-wavelength structure at the target temperature of 60 °C when the minimum structure line width limit of the process is ignored. Obviously, the IRA can be enhanced when the SHAs are considered in active area of the thermopile device and the structural optimization of the SHAs is absolutely necessary.

scholarly journals Analysis of Optical Integration between Si3N4 Waveguide and a Ge-Based Optical Modulator Using a Lateral Amorphous GeSi Taper at the Telecommunication Wavelength of 1.55 µm

2019 ◽  
Vol 9 (18) ◽  
pp. 3846
Author(s):  
Worawat Traiwattanapong ◽  
Kazumi Wada ◽  
Papichaya Chaisakul
Keyword(s):  
Low Voltage ◽  
Extinction Ratio ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Fdtd Simulation ◽  
Optical Modulator ◽  
Optical Modulators ◽  
Optical Wavelength ◽  
Mode Size ◽  
Small Footprint

We report on the theoretical investigation of using an amorphous Ge0.83Si0.17 lateral taper to enable a low-loss small-footprint optical coupling between a Si3N4 waveguide and a low-voltage Ge-based Franz–Keldysh optical modulator on a bulk Si substrate using 3D Finite-Difference Time-Domain (3D-FDTD) simulation at the optical wavelength of 1550 nm. Despite a large refractive index and optical mode size mismatch between Si3N4 and the Ge-based modulator, the coupling structure rendered a good coupling performance within fabrication tolerance of advanced complementary metal-oxide semiconductor (CMOS) processes. For integrated optical modulator performance, the Si3N4-waveguide-integrated Ge-based on Si optical modulators could simultaneously provide workable values of extinction ratio (ER) and insertion loss (IL) for optical interconnect applications with a compact footprint.

Open Circuit Voltage and Single Walled Carbon Nanotube (wt%) Dependency in Solid-State Complementary Metal Oxide Semiconductor-Compatible Glucose Fuel Cells

2020 ◽  
Vol 12 (1) ◽  
pp. 101-106
Author(s):  
Md. Zahidul Islam ◽  
Shigeki Arata ◽  
Kenya Hayashi ◽  
Atsuki Kobayashi ◽  
Kiichi Niitsu
Keyword(s):  
Carbon Nanotube ◽  
Fuel Cell ◽  
Open Circuit Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Open Circuit ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Single Walled Carbon Nanotube ◽  
Single Walled Carbon ◽  
Cmos Compatible

Solid-state complementary metal oxide semiconductor (CMOS)-compatible glucose fuel cells, with single-walled carbon nanotube (SWCNT) films and different amounts of carbon nanotube (wt%) were investigated. Those with a SWCNT content of 3 wt% were found to develop the highest open circuit voltage (OCV) of 400 mV, together with a high electrical conductivity, a power density of 0.53 μW/cm2 and current density of 1.31 μA/cm2. Measurements were performed by dipping the anode into a 30 mM glucose solution. The OCV and power density increased together with the fuel cell concentration. The developed fuel cell uses materials that are biocompatible with the human body (single-walled carbon nanotube-glucose). As a result, it was possible to attain an OCV of 400 mV with a single-walled carbon nanotube content of 3 wt% while improvements in the performance of the CMOS-compatible glucose fuel cell were obtained, and the parameters affecting the performance of the fuel cell were identified. This bio-fuel cell was fabricated using CMOS semiconductor processes on a silicon wafer. These findings are significant to realizing mobile or implantable devices that can be used for biomedical applications.

A CMOS Compatible Metal-Polymer Microchannel Heat Sink for Monolithic Chip Cooling Applications

2010 ◽  
Author(s):  
Aziz Koyuncuog˘lu ◽  
Tuba Okutucu ◽  
Haluk Ku¨lah
Keyword(s):  
Heat Sink ◽  
Complementary Metal Oxide Semiconductor ◽  
Heat Sinks ◽  
Oxide Semiconductor ◽  
Microchannel Heat Sink ◽  
Liquid Cooling ◽  
Chip Cooling ◽  
Electronic Circuitry ◽  
Cmos Compatible ◽  
Adjacent Channels

A novel complementary metal oxide semiconductor (CMOS) compatible microchannel heat sink is designed and fabricated for monolithic liquid cooling of electronic circuits. The microchannels are fabricated with full metal walls between adjacent channels with a polymer top layer for easy sealing and optical visibility of the channels. The use of polymer also provides flexibility in adjusting the width of the channels allowing better management of the pressure drop. The proposed microchannel heat sink requires no design change of the electronic circuitry underneath, hence, can be produced by adding a few more steps to the standard CMOS fabrication flow. The microchannel heat sinks were tested successfully under various heat flux and coolant flow rate conditions. The preliminary cooling tests indicate that the proposed design is promising as a monolithic liquid cooling solution for CMOS circuits.

scholarly journals CMOS-compatible photonic devices for single-photon generation

Nanophotonics ◽  
2016 ◽  
Vol 5 (3) ◽  
pp. 427-439 ◽  
Author(s):  
Chunle Xiong ◽  
Bryn Bell ◽  
Benjamin J. Eggleton
Keyword(s):  
Secure Communication ◽  
Single Photon ◽  
Complementary Metal Oxide Semiconductor ◽  
Building Blocks ◽  
Photonic Devices ◽  
Oxide Semiconductor ◽  
Single Photons ◽  
Quantum Secure Communication ◽  
Cmos Compatible ◽  
Photon Generation

AbstractSources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

A Complementary Metal Oxide Semiconductor (CMOS) Compatible Capacitive Silicon Accelerometer with Polysilicon Rib-Style Flexures

1998 ◽  
Vol 37 (Part 1, No. 12B) ◽  
pp. 7093-7099 ◽  
Author(s):  
Seokyu Kim ◽  
Youngjoo Yee ◽  
Hyeoncheol Kim ◽  
Kukjin Chun ◽  
Ikpyo Hong ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Compatible

Vertical Arrays of Copper Nanotube Grown on Silicon Substrate by CMOS Compatible Electrochemical Process for IC Packaging Applications

2009 ◽  
Vol 6 (3) ◽  
pp. 154-157
Author(s):  
Daniel Choi ◽  
Viola Fucsko ◽  
E. H. Yang ◽  
Jung-Rae Park ◽  
Fahad Khalid ◽  
...  
Keyword(s):  
Thermal Conductivity ◽  
Integrated Circuit ◽  
High Surface ◽  
Complementary Metal Oxide Semiconductor ◽  
Electrochemical Process ◽  
Oxide Semiconductor ◽  
Cu Nanowires ◽  
Vertical Arrays ◽  
Ic Packaging ◽  
Cmos Compatible

We present an electrodeposition-based fabrication process which can be complementary metal oxide semiconductor (CMOS) compatible for creating vertical arrays of copper (Cu) nanotubes for integrated circuit (IC) packaging applications. Since such nanotube structures offer high surface-to-volume ratios, low resistivity, and high thermal conductivity, they are especially suited for IC packaging applications requiring efficient heat transfer as well as electrical interconnect applications. In this work, Cu nanotube arrays were electrodeposited into alumina nanopore templates with pore diameters of approximately 50 nm and 100 nm. Simulation and measurements of the vertical arrays of Cu nanotubes showed greatly enhanced thermal conductivity in the direction of nanotube alignment compared with Cu nanowires and bulk Cu. The thermal conductivity of the vertical arrays of Cu nanotubes at 100°C is about 0.35W/m · K compared to the 0.24 W/m · K from Cu bulk materials, which shows an enhancement of about 146% as a result of the more efficient thermal conduction in Cu nanotubes.

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