Vertical Arrays of Copper Nanotube Grown on Silicon Substrate by CMOS Compatible Electrochemical Process for IC Packaging Applications

2009 ◽  
Vol 6 (3) ◽  
pp. 154-157
Author(s):  
Daniel Choi ◽  
Viola Fucsko ◽  
E. H. Yang ◽  
Jung-Rae Park ◽  
Fahad Khalid ◽  
...  
Keyword(s):  
Thermal Conductivity ◽  
Integrated Circuit ◽  
High Surface ◽  
Complementary Metal Oxide Semiconductor ◽  
Electrochemical Process ◽  
Oxide Semiconductor ◽  
Cu Nanowires ◽  
Vertical Arrays ◽  
Ic Packaging ◽  
Cmos Compatible

We present an electrodeposition-based fabrication process which can be complementary metal oxide semiconductor (CMOS) compatible for creating vertical arrays of copper (Cu) nanotubes for integrated circuit (IC) packaging applications. Since such nanotube structures offer high surface-to-volume ratios, low resistivity, and high thermal conductivity, they are especially suited for IC packaging applications requiring efficient heat transfer as well as electrical interconnect applications. In this work, Cu nanotube arrays were electrodeposited into alumina nanopore templates with pore diameters of approximately 50 nm and 100 nm. Simulation and measurements of the vertical arrays of Cu nanotubes showed greatly enhanced thermal conductivity in the direction of nanotube alignment compared with Cu nanowires and bulk Cu. The thermal conductivity of the vertical arrays of Cu nanotubes at 100°C is about 0.35W/m · K compared to the 0.24 W/m · K from Cu bulk materials, which shows an enhancement of about 146% as a result of the more efficient thermal conduction in Cu nanotubes.

scholarly journals Low-Cost Microbolometer Type Infrared Detectors

Micromachines ◽  
2020 ◽  
Vol 11 (9) ◽  
pp. 800
Author(s):  
Le Yu ◽  
Yaozu Guo ◽  
Haoyu Zhu ◽  
Mingcheng Luo ◽  
Ping Han ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Focal Plane ◽  
Technological Development ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Micro Electro Mechanical System ◽  
Focal Plane Arrays ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Cmos Compatible

The complementary metal oxide semiconductor (CMOS) microbolometer technology provides a low-cost approach for the long-wave infrared (LWIR) imaging applications. The fabrication of the CMOS-compatible microbolometer infrared focal plane arrays (IRFPAs) is based on the combination of the standard CMOS process and simple post-CMOS micro-electro-mechanical system (MEMS) process. With the technological development, the performance of the commercialized CMOS-compatible microbolometers shows only a small gap with that of the mainstream ones. This paper reviews the basics and recent advances of the CMOS-compatible microbolometer IRFPAs in the aspects of the pixel structure, the read-out integrated circuit (ROIC), the focal plane array, and the vacuum packaging.

scholarly journals Effects of Process Variations in a HCMOS IC using a Monte Carlo SPICE Simulation

2017 ◽  
pp. 11-16
Author(s):  
Widianto Widianto ◽  
Lailis Syafaah ◽  
Nurhadi Nurhadi
Keyword(s):  
Monte Carlo ◽  
Integrated Circuit ◽  
High Speed ◽  
Evaluation Method ◽  
Complementary Metal Oxide Semiconductor ◽  
Process Variations ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Spice Simulation ◽  
Simulation Results

In this paper, effects of process variations in a HCMOS (High-Speed Complementary Metal Oxide Semiconductor) IC (Integrated Circuit) are examined using a Monte Carlo SPICE (Simulation Program with Integrated Circuit Emphasis) simulation. The variations of the IC are L and VTO variations. An evaluation method is used to evaluate the effects of the variations by modeling it using a normal (Gaussian) distribution. The simulation results show that the IC may be detected as a defective IC caused by the variations based on large supply currents flow to it. 

scholarly journals Angular Light, Polarization and Stokes Parameters Information in a Hybrid Image Sensor with Division of Focal Plane

Sensors ◽  
2020 ◽  
Vol 20 (12) ◽  
pp. 3391
Author(s):  
Francelino Freitas Carvalho ◽  
Carlos Augusto de Moraes Cruz ◽  
Greicy Costa Marques ◽  
Kayque Martins Cruz Damasceno
Keyword(s):  
Integrated Circuit ◽  
Incident Angle ◽  
Complementary Metal Oxide Semiconductor ◽  
Image Sensor ◽  
Light Polarization ◽  
Oxide Semiconductor ◽  
Stokes Parameters ◽  
New Paradigm ◽  
Depth Sensing ◽  
3D Image Reconstruction

Targeting 3D image reconstruction and depth sensing, a desirable feature for complementary metal oxide semiconductor (CMOS) image sensors is the ability to detect local light incident angle and the light polarization. In the last years, advances in the CMOS technologies have enabled dedicated circuits to determine these parameters in an image sensor. However, due to the great number of pixels required in a cluster to enable such functionality, implementing such features in regular CMOS imagers is still not viable. The current state-of-the-art solutions require eight pixels in a cluster to detect local light intensity, incident angle and polarization. The technique to detect local incident angle is widely exploited in the literature, and the authors have shown in previous works that it is possible to perform the job with a cluster of only four pixels. In this work, the authors explore three novelties: a mean to determine three of four Stokes parameters, the new paradigm in polarization cluster-pixel design, and the extended ability to detect both the local light angle and intensity. The features of the proposed pixel cluster are demonstrated through simulation program with integrated circuit emphasis (SPICE) of the regular Quadrature Pixel Cluster and Polarization Pixel Cluster models, the results of which are compliant with experimental results presented in the literature.

scholarly journals A 45 nm CMOS Avalanche Photodiode with 8.4-GHz Bandwidth

Micromachines ◽  
2020 ◽  
Vol 11 (1) ◽  
pp. 65
Author(s):  
Wenhao Zhi ◽  
Qingxiao Quan ◽  
Pingping Yu ◽  
Yanfeng Jiang
Keyword(s):  
Optical Communication ◽  
Integrated Circuit ◽  
Communication Systems ◽  
Complementary Metal Oxide Semiconductor ◽  
Avalanche Photodiode ◽  
Cmos Technology ◽  
Optical Signal ◽  
Oxide Semiconductor ◽  
Monolithically Integrated ◽  
Process Modification

Photodiode is one of the key components in optoelectronic technology, which is used to convert optical signal into electrical ones in modern communication systems. In this paper, an avalanche photodiode (APD) is designed and fulfilled, which is compatible with Taiwan Semiconductor Manufacturing Company (TSMC) 45-nm standard complementary metal–oxide–semiconductor (CMOS) technology without any process modification. The APD based on 45 nm process is beneficial to realize a smaller and more complex monolithically integrated optoelectronic chip. The fabricated CMOS APD operates at 850 nm wavelength optical communication. Its bandwidth can be as high as 8.4 GHz with 0.56 A/W responsivity at reverse bias of 20.8 V. Its active area is designed to be 20 × 20 μm2. The Simulation Program with Integrated Circuit Emphasis (SPICE) model of the APD is also proposed and verified. The key parameters are extracted based on its electrical, optical and frequency responses by parameter fitting. The device has wide potential application for optical communication systems.

scholarly journals Monolithic optoelectronic integrated broadband optical receiver with graphene photodetectors

Nanophotonics ◽  
2017 ◽  
Vol 6 (6) ◽  
pp. 1343-1352 ◽  
Author(s):  
Chuantong Cheng ◽  
Beiju Huang ◽  
Xurui Mao ◽  
Zanyun Zhang ◽  
Zan Zhang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Cost ◽  
Three Dimensional ◽  
Complementary Metal Oxide Semiconductor ◽  
Optical Signal ◽  
Optical Interconnect ◽  
Optical Receiver ◽  
Oxide Semiconductor ◽  
Experimental Realization ◽  
Operation Speed

AbstractOptical receivers with potentially high operation bandwidth and low cost have received considerable interest due to rapidly growing data traffic and potential Tb/s optical interconnect requirements. Experimental realization of 65 GHz optical signal detection and 262 GHz intrinsic operation speed reveals the significance role of graphene photodetectors (PDs) in optical interconnect domains. In this work, a novel complementary metal oxide semiconductor post-backend process has been developed for integrating graphene PDs onto silicon integrated circuit chips. A prototype monolithic optoelectronic integrated optical receiver has been successfully demonstrated for the first time. Moreover, this is a firstly reported broadband optical receiver benefiting from natural broadband light absorption features of graphene material. This work is a perfect exhibition of the concept of monolithic optoelectronic integration and will pave way to monolithically integrated graphene optoelectronic devices with silicon ICs for three-dimensional optoelectronic integrated circuit chips.

scholarly journals Fully Differential Chopper-Stabilized Multipath Current-Feedback Instrumentation Amplifier with R-2R DAC Offset Adjustment for Resistive Bridge Sensors

2019 ◽  
Vol 10 (1) ◽  
pp. 63 ◽  
Author(s):  
Yongsu Kwon ◽  
Hyungseup Kim ◽  
Jaesung Kim ◽  
Kwonsang Han ◽  
Donggeun You ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Current Feedback ◽  
Readout Integrated Circuit ◽  
Fully Differential ◽  
Chopper Stabilization ◽  
Rejection Ratio

A fully differential multipath current-feedback instrumentation amplifier (CFIA) for a resistive bridge sensor readout integrated circuit (IC) is proposed. To reduce the CFIA’s own offset and 1/f noise, a chopper stabilization technique is implemented. To attenuate the output ripple caused by chopper up-modulation, a ripple reduction loop (RRL) is employed. A multipath architecture is implemented to compensate for the notch in the chopping frequency band of the transfer function. To prevent performance degradation resulting from external offset, a 12-bit R-2R digital-to-analog converter (DAC) is employed. The proposed CFIA has an adjustable gain of 16–44 dB with 5-bit programmable resistors. The proposed resistive sensor readout IC is implemented in a 0.18 μm complementary metal-oxide-semiconductor (CMOS) process. The CFIA draws 169 μA currents from a 3.3 V supply. The simulated input-referred noise and noise efficiency factor (NEF) are 28.3 nV/√Hz and 14.2, respectively. The simulated common-mode rejection ratio (CMRR) is 162 dB, and the power supply rejection ratio (PSRR) is 112 dB.

Sign in / Sign up

Export Citation Format

Share Document