scholarly journals CMOS-compatible photonic devices for single-photon generation

Nanophotonics ◽  
2016 ◽  
Vol 5 (3) ◽  
pp. 427-439 ◽  
Author(s):  
Chunle Xiong ◽  
Bryn Bell ◽  
Benjamin J. Eggleton
Keyword(s):  
Secure Communication ◽  
Single Photon ◽  
Complementary Metal Oxide Semiconductor ◽  
Building Blocks ◽  
Photonic Devices ◽  
Oxide Semiconductor ◽  
Single Photons ◽  
Quantum Secure Communication ◽  
Cmos Compatible ◽  
Photon Generation

AbstractSources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

Controlled quantum secure communication protocol with single photons in both polarization and spatial-mode degrees of freedom

2016 ◽  
Vol 30 (05) ◽  
pp. 1650051 ◽  
Author(s):  
Lili Wang ◽  
Wenping Ma
Keyword(s):  
Secure Communication ◽  
Degrees Of Freedom ◽  
Communication Protocol ◽  
Single Photon ◽  
Quantum Secure Direct Communication ◽  
Single Photons ◽  
Spatial Mode ◽  
The Third ◽  
Quantum Secure Communication ◽  
The Cost

In this paper, we propose a new controlled quantum secure direct communication (CQSDC) protocol with single photons in both polarization and spatial-mode degrees of freedom. Based on the defined local collective unitary operations, the sender’s secret messages can be transmitted directly to the receiver through encoding secret messages on the particles. Only with the help of the third side, the receiver can reconstruct the secret messages. Each single photon in two degrees of freedom can carry two bits of information, so the cost of our protocol is less than others using entangled qubits. Moreover, the security of our QSDC network protocol is discussed comprehensively. It is shown that our new CQSDC protocol cannot only defend the outsider eavesdroppers’ several sorts of attacks but also the inside attacks. Besides, our protocol is feasible since the preparation and the measurement of single photon quantum states in both the polarization and the spatial-mode degrees of freedom are available with current quantum techniques.

scholarly journals Phase Change Metasurfaces by Continuous or Quasi-Continuous Atoms for Active Optoelectronic Integration

Materials ◽  
2021 ◽  
Vol 14 (5) ◽  
pp. 1272
Author(s):  
Zhihua Fan ◽  
Qinling Deng ◽  
Xiaoyu Ma ◽  
Shaolin Zhou
Keyword(s):  
Phase Change ◽  
Phase Change Materials ◽  
Complementary Metal Oxide Semiconductor ◽  
Photonic Devices ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Nanophotonic Devices ◽  
Optoelectronic Integration ◽  
Hybrid Devices ◽  
Micro Electromechanical System

In recent decades, metasurfaces have emerged as an exotic and appealing group of nanophotonic devices for versatile wave regulation with deep subwavelength thickness facilitating compact integration. However, the ability to dynamically control the wave–matter interaction with external stimulus is highly desirable especially in such scenarios as integrated photonics and optoelectronics, since their performance in amplitude and phase control settle down once manufactured. Currently, available routes to construct active photonic devices include micro-electromechanical system (MEMS), semiconductors, liquid crystal, and phase change materials (PCMs)-integrated hybrid devices, etc. For the sake of compact integration and good compatibility with the mainstream complementary metal oxide semiconductor (CMOS) process for nanofabrication and device integration, the PCMs-based scheme stands out as a viable and promising candidate. Therefore, this review focuses on recent progresses on phase change metasurfaces with dynamic wave control (amplitude and phase or wavefront), and especially outlines those with continuous or quasi-continuous atoms in favor of optoelectronic integration.

scholarly journals High Dynamic Range Imaging with TDC-Based CMOS SPAD Arrays

Instruments ◽  
2019 ◽  
Vol 3 (3) ◽  
pp. 38 ◽  
Author(s):  
Majid Zarghami ◽  
Leonardo Gasparini ◽  
Matteo Perenzoni ◽  
Lucio Pancheri
Keyword(s):  
Dynamic Range ◽  
Single Photon ◽  
Photon Counting ◽  
Complementary Metal Oxide Semiconductor ◽  
High Dynamic Range ◽  
Oxide Semiconductor ◽  
Photon Flux ◽  
Integration Time ◽  
Rate Dependent ◽  
High Dynamic

This paper investigates the use of image sensors based on complementary metal–oxide–semiconductor (CMOS) single-photon avalanche diodes (SPADs) in high dynamic range (HDR) imaging by combining photon counts and timestamps. The proposed method is validated experimentally with an SPAD detector based on a per-pixel time-to-digital converter (TDC) architecture. The detector, featuring 32 × 32 pixels with 44.64-µm pitch, 19.48% fill factor, and time-resolving capability of ~295-ps, was fabricated in a 150-nm CMOS standard technology. At high photon flux densities, the pixel output is saturated when operating in photon-counting mode, thus limiting the DR of this imager. This limitation can be overcome by exploiting the distribution of photon arrival times in each pixel, which shows an exponential behavior with a decay rate dependent on the photon flux level. By fitting the histogram curve with the exponential decay function, the extracted time constant is used to estimate the photon count. This approach achieves 138.7-dB dynamic range within 30-ms of integration time, and can be further extended by using a timestamping mechanism with a higher resolution.

scholarly journals Photon-Detection-Probability Simulation Method for CMOS Single-Photon Avalanche Diodes

Sensors ◽  
2020 ◽  
Vol 20 (2) ◽  
pp. 436 ◽  
Author(s):  
Chin-An Hsieh ◽  
Chia-Ming Tsai ◽  
Bing-Yue Tsui ◽  
Bo-Jen Hsiao ◽  
Sheng-Di Lin
Keyword(s):  
Detection Probability ◽  
Single Photon ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Single Photons ◽  
Photon Detection ◽  
Important Indicator ◽  
Avalanche Diodes ◽  
Single Photon Avalanche Diodes

Single-photon avalanche diodes (SPADs) in complementary metal-oxide-semiconductor (CMOS) technology have excellent timing resolution and are capable to detect single photons. The most important indicator for its sensitivity, photon-detection probability (PDP), defines the probability of a successful detection for a single incident photon. To optimize PDP is a cost- and time-consuming task due to the complicated and expensive CMOS process. In this work, we have developed a simulation procedure to predict the PDP without any fitting parameter. With the given process parameters, our method combines the process, the electrical, and the optical simulations in commercially available software and the calculation of breakdown trigger probability. The simulation results have been compared with the experimental data conducted in an 800-nm CMOS technology and obtained a good consistence at the wavelength longer than 600 nm. The possible reasons for the disagreement at the short wavelength have been discussed. Our work provides an effective way to optimize the PDP of a SPAD prior to its fabrication.

scholarly journals Modeling, Simulation Methods and Characterization of Photon Detection Probability in CMOS-SPAD

Sensors ◽  
2021 ◽  
Vol 21 (17) ◽  
pp. 5860
Author(s):  
Aymeric Panglosse ◽  
Philippe Martin-Gonthier ◽  
Olivier Marcelot ◽  
Cédric Virmontois ◽  
Olivier Saint-Pé ◽  
...  
Keyword(s):  
Detection Probability ◽  
Computer Aided Design ◽  
Single Photon ◽  
Complementary Metal Oxide Semiconductor ◽  
Simulation Method ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Doping Profile ◽  
Cmos Process ◽  
Photon Detection

Single-Photon Avalanche Diodes (SPAD) in Complementary Metal-Oxide Semiconductor (CMOS) technology are potential candidates for future “Light Detection and Ranging” (Lidar) space systems. Among the SPAD performance parameters, the Photon Detection Probability (PDP) is one of the principal parameters. Indeed, this parameter is used to evaluate the SPAD sensitivity, which directly affects the laser power or the telescope diameter of space-borne Lidars. In this work, we developed a model and a simulation method to predict accurately the PDP of CMOS SPAD, based on a combination of measurements to acquire the CMOS process doping profile, Technology Computer-Aided Design (TCAD) simulations, and a Matlab routine. We compare our simulation results with a SPAD designed and processed in CMOS 180 nm technology. Our results show good agreement between PDP predictions and measurements, with a mean error around 18.5%, for wavelength between 450 and 950 nm and for a typical range of excess voltages between 15 and 30% of the breakdown voltage. Due to our SPAD architecture, the high field region is not entirely insulated from the substrate, a comparison between simulations performed with and without the substrate contribution indicates that PDP can be simulated without this latter with a moderate loss of precision, around 4.5 percentage points.

scholarly journals Low Temperature Sensitivity CMOS Transconductor Based on GZTC MOSFET Condition

2016 ◽  
Vol 11 (1) ◽  
pp. 27-37
Author(s):  
Pedro Toledo ◽  
Hamilton Klimach ◽  
David Cordova ◽  
Sergio Bampi ◽  
Eric Fabris
Keyword(s):  
Analog Circuits ◽  
Thermal Sensitivity ◽  
Temperature Stability ◽  
Complementary Metal Oxide Semiconductor ◽  
Building Blocks ◽  
Oxide Semiconductor ◽  
Zero Temperature ◽  
Strong Inversion ◽  
Commercial Process ◽  
Bias Condition

Complementary Metal Oxide Semiconductor (CMOS) Transconductors, or Gm cells, are key building blocks to implement a large variety of analog circuits such as adjustable filters, multipliers, controlled oscillators and amplifiers. Usually temperature stability is a must in such applications, and herein we define all required conditions to design low thermal sensitivity Gm cells by biasing MOSFETs at Transconductance Zero Temperature Condition (GZTC). This special bias condition is analyzed using a MOSFET model which is continuous from weak to strong inversion, and it is proved that this condition always occurs from moderate to strong inversion operation in any CMOS fabrication process. Additionally, a few example circuits are designed using this technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits have been simulated in a 130 nm CMOS commercial process, resulting in improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/oC.

scholarly journals An Advanced 1-bit Arithmetic Logic Unit (ALU) with Hybrid Memristor-CMOS Architecture

2021 ◽  
Author(s):  
Muhammad Farhan Azmine ◽  
Urmi Debnath ◽  
Yeasir Arafat
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Building Blocks ◽  
Oxide Semiconductor ◽  
Memory Element ◽  
Area Efficiency ◽  
Arithmetic Logic Unit ◽  
Non Volatile Memory ◽  
Electrical Component ◽  
Logic Unit

<div>Memristor is dubbed as the fourth fundamental electrical component which works primarily as a non-volatile memory element. Memristors can also be used to construct logic gates, and Memristor Ratioed Logic (MRL) is one of these structures. The higher area efficiency and CMOS architecture compatibility of MRL gates have lead researchers to pay attention to its use in digital logic architecture. In this work, binary MRL is integrated with Complementary Metal-Oxide Semiconductor(CMOS) logic elements to develop building blocks of an Arithmetic Logic Unit (ALU). The proposed 1-bit ALU is simulated using LTSpice, which allows the versatility of changing the parameters as per the model used. This work designs and analyses an optimized cascadable 1-bit ALU with with voltage level based binary logic state via simulation. The proposed circuit shows improvement in transistor count and delay over benchmark circuits.</div>

scholarly journals Fast-Gated 16 × 1 SPAD Array for Non-Line-of-Sight Imaging Applications

Instruments ◽  
2020 ◽  
Vol 4 (2) ◽  
pp. 14
Author(s):  
Marco Renna ◽  
Ji Hyun Nam ◽  
Mauro Buttafava ◽  
Federica Villa ◽  
Andreas Velten ◽  
...  
Keyword(s):  
Single Photon ◽  
Photon Counting ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Line Of Sight ◽  
Single Photon Detector ◽  
Single Photon Counting ◽  
Timing Resolution ◽  
Fast Gating ◽  
Non Line Of Sight

In this paper we present a novel single-photon detector specifically designed for Non-Line-Of-Sight (NLOS) imaging applications within the framework of the DARPA REVEAL program. The instrument is based on a linear 16 × 1 Complementary Metal-Oxide-Semiconductor (CMOS) Single-Photon Avalanche Diode (SPAD) array operated in fast-gated mode by a novel fast-gating Active Quenching Circuit (AQC) array, which enables the detectors with sub-ns transitions thanks to a SPAD-dummy approach. The detector exhibits a timing resolution better than 50 ps (Full Width at Half Maximum - FWHM) at a measurement repetition rate up to 40 MHz, and provides 16 independent outputs compatible with commercial Time-Correlated Single-Photon Counting (TCSPC) instrumentation. The instrument has been experimentally characterized and operated in preliminary NLOS imaging acquisitions where a 40 × 60 cm hidden object is successfully reconstructed by scanning over a grid of 150 × 150 positions.

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