scholarly journals Synthesis Strategy of Reversible Circuits on DNA Computers

Symmetry ◽  
2021 ◽  
Vol 13 (7) ◽  
pp. 1242
Author(s):  
Mirna Rofail ◽  
Ahmed Younes
Keyword(s):  
Average Length ◽  
Logic Gates ◽  
Building Blocks ◽  
Quantum Cost ◽  
Reversible Circuits ◽  
Synthesis Strategy ◽  
Reversible Gate ◽  
Displacement Reactions ◽  
Reversible Logic Gates ◽  
Dna Computers

DNA computers and quantum computers are gaining attention as alternatives to classical digital computers. DNA is a biological material that can be reprogrammed to perform computing functions. Quantum computing performs reversible computations by nature based on the laws of quantum mechanics. In this paper, DNA computing and reversible computing are combined to propose novel theoretical methods to implement reversible gates and circuits in DNA computers based on strand displacement reactions, since the advantages of reversible logic gates can be exploited to improve the capabilities and functionalities of DNA computers. This paper also proposes a novel universal reversible gate library (URGL) for synthesizing n-bit reversible circuits using DNA to reduce the average length and cost of the constructed circuits when compared with previous methods. Each n-bit URGL contains building blocks to generate all possible permutations of a symmetric group of degree n. Our proposed group (URGL) in the paper is a permutation group. The proposed implementation methods will improve the efficiency of DNA computer computations as the results of DNA implementations are better in terms of quantum cost, DNA cost, and circuit length.

scholarly journals A review on reversible logic gates

2020 ◽  
Vol 12 (1) ◽  
pp. 242-250
Author(s):  
B.Y. Galadima ◽  
G.S.M. Galadanci ◽  
A. Tijjani ◽  
M. Ibrahim
Keyword(s):  
Digital Signal ◽  
Logic Gates ◽  
Propagation Delay ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Hardware Complexity ◽  
Nano Technology ◽  
Reversible Circuits ◽  
Comparative Review ◽  
Reversible Logic Gates

In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, optical information processing, quantum computing and nano technology. Reversibility plays an important role when computations with minimal energy dissipation are considered. The main purpose of designing reversible logic is to decrease the number of reversible gates, garbage outputs, constant inputs, quantum cost, area, power, delay and hardware complexity of the reversible circuits. This paper reveals a comparative review on various reversible logic gates. This paper provides some reversible logic gates, which can be used in designing more complex systems having reversible circuits and can execute more complicated operations using quantum computers. Future digital technology will use reversible logic gates in order to reduce the power consumption and propagation delay as it effectively provides negligible loss of information in the circuit.   Keywords: Garbage output, Power dissipation, quantum cost, Reversible Gate, Reversible logic,

Design of Combinational Circuits Using Reversible Decoder in Tanner Tools

2020 ◽  
Vol 17 (4) ◽  
pp. 1743-1751
Author(s):  
R. Kannan ◽  
K. Vidhya
Keyword(s):  
Low Power ◽  
Optical Computing ◽  
Logic Gates ◽  
Full Adder ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Combinational Circuits ◽  
Nano Technology ◽  
Feynman Gate ◽  
Reversible Logic Gates

Reversible logic is the emerging field for research in present era. The aim of this paper is to realize different types of combinational circuits like full-adder, full-subtractor, multiplexer and comparator using reversible decoder circuit with minimum quantum cost. Reversible decoder is designed using Fredkin gates with minimum Quantum cost. There are many reversible logic gates like Fredkin Gate, Feynman Gate, Double Feynman Gate, Peres Gate, Seynman Gate and many more. Reversible logic is defined as the logic in which the number output lines are equal to the number of input lines i.e., the n-input and k-output Boolean function F(X1,X2,X3, ...,Xn) (referred to as (n,k) function) is said to be reversible if and only if (i) n is equal to k and (ii) each input pattern is mapped uniquely to output pattern. The gate must run forward and backward that is the inputs can also be retrieved from outputs. When the device obeys these two conditions then the second law of thermo-dynamics guarantees that it dissipates no heat. Fan-out and Feed-back are not allowed in Logical Reversibility. Reversible Logic owns its applications in various fields which include Quantum Computing, Optical Computing, Nano-technology, Computer Graphics, low power VLSI etc. Reversible logic is gaining its own importance in recent years largely due to its property of low power consumption. The comparative study in terms of garbage outputs, Quantum Cost, numbers of gates are also presented. The Circuit has been implemented and simulated using Tannaer tools v15.0 software.

Estimation of Power for Reversible Subtractors

2018 ◽  
Vol 7 (4.5) ◽  
pp. 102
Author(s):  
E. V.Naga Lakshmi ◽  
Dr. N.Siva Sankara Reddy
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Logic Gates ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Gate Count ◽  
Garbage Output ◽  
Reversible Logic Gates

In recent years Reversible Logic Circuits (RLC) are proved to be more efficient in terms of power dissipation. Hence, most of the researchers developed Reversible logic circuits for low power applications. RLC are designed with the help of Reversible Logic Gates (RLG).   Efficiency of the Reversible gates is measured in terms of Quantum cost, gate count, garbage output lines, logic depth and constant inputs. In this paper, measurement of power for RLG is done. Basic RLGs are designed using GDI technology and compared in terms of power dissipation. 1 bit Full subtractor is designed using EVNL gate [1] and also with TG& Fy [6] gates. The power dissipation is compared with 1 bit TR gate [5] full subtractor.  Then 2 bit, 4 bit and 8 bit subtractors are designed and compared the powers. Proposed 4 bit and 8 bit full subtractors are dissipating less power when compared to TR gate 4 bit and 8 bit subtractors.  

scholarly journals Design Multipurpose Circuits with Minimum Garbage Outputs Using CMVMIN Gate

2014 ◽  
Vol 2014 ◽  
pp. 1-7 ◽  
Author(s):  
Bahram Dehghan
Keyword(s):  
Logic Gates ◽  
Quantum Cost ◽  
Computing Paradigm ◽  
Novel Approach ◽  
Half Adder ◽  
Majority Voter ◽  
Garbage Output ◽  
Reversible Logic Gates ◽  
Novel Design

Quantum-dot cellular automata (QCA) suggest an emerging computing paradigm for nanotechnology. The QCA offers novel approach in electronics for information processing and communication. QCA have recently become the focus of interest in the field of low power nanocomputing and nanotechnology. The fundamental logic elements of this technology are the majority voter (MV) and the inverter (INV). This paper presents a novel design with less garbage output and minimum quantum cost in nanotechnology. In the paper we show how to create multipurpose reversible gates. By development of suitable gates in logic circuits as an example, we can combine MFA and HS in one design using CMVMIN gate. We offer CMVMIN gate implementations to be used in multipurpose circuit. We can produce concurrent half adder/subtractor and one bit comparator in one design using reversible logic gates and CMVMIN gates. Also, a 2×4 decoder from recent architecture has been shown independently. We investigate the result of the proposed design using truth table. A significant improvement in quality of the calculated parameters and variety of required outputs has been achieved.

scholarly journals High functionality reversible arithmetic logic unit

2020 ◽  
Vol 10 (3) ◽  
pp. 2329
Author(s):  
Shaveta Thakral ◽  
Dipali Bansal
Keyword(s):  
Power Dissipation ◽  
Logic Gates ◽  
Reversible Logic ◽  
Logic Design ◽  
Quantum Cost ◽  
Verilog Hdl ◽  
Power Efficient ◽  
Reversible Logic Gates ◽  
Reversible Alu ◽  
Logic Unit

Energy loss is a big challenge in digital logic design primarily due to impending end of Moore’s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are limited. The main aim of this paper is to propose a new design of reversible ALU and enhance number of operations in it. This paper critically analyzes proposed ALU with existing designs and demonstrates increase in functionality with 56% reduction in gates, 17 % reduction in garbage lines, 92 % reduction in ancillary lines and 53 % reduction in quantum cost. The proposed ALU design is coded in Verilog HDL, synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2. RCViewer+ tool has been used to validate quantum cost of proposed design.

Novel design of multiplexer and demultiplexer using reversible logic gates

2018 ◽  
Vol 7 (3.29) ◽  
pp. 80
Author(s):  
Veerendra Nath Nune ◽  
Addanki Purna R
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Logic Gates ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Gate Count ◽  
Reversible Logic Gates ◽  
Novel Design

Reversibility is the prominent technology in the recent era. In reversible logic the number output lines are equal to the number of input lines. In reversible logic the inputs are to be retrieved from the outputs. Reversible logic gates are user defined gates. Reversible logic owns its applications in various fields which include low power VLSI. In this paper multiplexer is implemented using QCA, SAM and QCA & SAM gate. Also demultiplexer is implemented using two new reversible logic gates RAMESH and RAMESH-1 gates. These designs are simulated and synthesized using Xilinx ISE 12.1 and Mentor Graphics tool. The result shows that the proposed designs are more efficient in terms of gate count, quantum cost and power consumption.  

ENERGY EFFICIENT REVERSIBLE BUILDING BLOCKS RESISTANT TO POWER ANALYSIS ATTACKS

2014 ◽  
Vol 23 (09) ◽  
pp. 1450127 ◽  
Author(s):  
P. SARAVANAN ◽  
P. KALPANA
Keyword(s):  
Power Analysis ◽  
Voltage Drop ◽  
Building Blocks ◽  
Propagation Delay ◽  
Input Stimulus ◽  
Power Analysis Attacks ◽  
Transmission Gate ◽  
Reversible Circuits ◽  
Reversible Gate ◽  
A Chain

Reversible logic circuits consist of a chain of reversible gates with many stages. The existing transmission gate-based implementation of reversible gates severely suffers from voltage degradation because of the inherent resistive voltage drop when cascaded. In addition, the propagation delay increases quadratically with the number of transmission gates cascaded in reversible circuits. To circumvent these problems in cascaded circuits, static CMOS buffers or latches are generally inserted at intermediate stages. But the static CMOS latches are inherently irreversible and cannot be used in reversible circuits. In this work, a novel adiabatic reversible latch is proposed to regenerate the voltage levels at intermediate stages in cascaded reversible circuits. The proposed latch is placed at the target line of each transmission gate-based reversible gate implementation to restore the logic to their respective voltage levels and at the same time reduces the energy consumption significantly. In addition, the proposed adiabatic reversible gate implementations show resistance against power analysis attacks as the current drawn from the power supply matches for all cases of input stimulus.

scholarly journals Optimization of Reversible Circuits Using Toffoli Decompositions with Negative Controls

Symmetry ◽  
2021 ◽  
Vol 13 (6) ◽  
pp. 1025
Author(s):  
Mariam Gado ◽  
Ahmed Younes
Keyword(s):  
Symmetric Group ◽  
Permutation Group ◽  
Building Blocks ◽  
Quantum Circuits ◽  
Quantum Computers ◽  
Quantum Cost ◽  
Reversible Circuits ◽  
Negative Controls ◽  
Target Qubit

The synthesis and optimization of quantum circuits are essential for the construction of quantum computers. This paper proposes two methods to reduce the quantum cost of 3-bit reversible circuits. The first method utilizes basic building blocks of gate pairs using different Toffoli decompositions. These gate pairs are used to reconstruct the quantum circuits where further optimization rules will be applied to synthesize the optimized circuit. The second method suggests using a new universal library, which provides better quantum cost when compared with previous work in both cost015 and cost115 metrics; this proposed new universal library “Negative NCT” uses gates that operate on the target qubit only when the control qubit’s state is zero. A combination of the proposed basic building blocks of pairs of gates and the proposed Negative NCT library is used in this work for synthesis and optimization, where the Negative NCT library showed better quantum cost after optimization compared with the NCT library despite having the same circuit size. The reversible circuits over three bits form a permutation group of size 40,320 (23!), which is a subset of the symmetric group, where the NCT library is considered as the generators of the permutation group.

Quantum cost optimized design of 4-bit reversible universal shift register using reduced number of logic gate

2018 ◽  
Vol 16 (02) ◽  
pp. 1850016 ◽  
Author(s):  
H. Maity ◽  
A. Biswas ◽  
A. K. Bhattacharjee ◽  
A. Pal
Keyword(s):  
Quantum Computing ◽  
Logic Gate ◽  
Logic Gates ◽  
Reversible Logic ◽  
Shift Register ◽  
Optimized Design ◽  
Quantum Cost ◽  
Universal Shift Register ◽  
Reversible Logic Gates

In this paper, we have proposed the design of quantum cost (QC) optimized 4-bit reversible universal shift register (RUSR) using reduced number of reversible logic gates. The proposed design is very useful in quantum computing due to its low QC, less no. of reversible logic gate and less delay. The QC, no. of gates, garbage outputs (GOs) are respectively 64, 8 and 16 for proposed work. The improvement of proposed work is also presented. The QC is 5.88% to 70.9% improved, no. of gate is 60% to 83.33% improved with compared to latest reported result.

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