scholarly journals FPGA Based Vector Control of Induction Motor

2020 ◽  
Vol 9 (4) ◽  
pp. 572-577
Keyword(s):  
Induction Motor ◽  
High Speed ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Electronic Industry ◽  
New Approach ◽  
The Past ◽  
Field Programmable ◽  
Signal Processors ◽  
Very High

To get the desired response of the sensor less Vector controlled Induction Motor (SVC-IM) by the experimental setup, the controller implementation for the generation of the PWM signals is the key role. It is possible with the rapid growth of electronic industry such as high speed digital signal processors (DSPs) with micro controllers available in the present market. In the past DSP technologies were used to realize the several SVC-IM schemes, i.e. KF, PI, GA and PSO respectively. However, it creates issues related to the time delay and execution of the PWM signals, etc., as a results system becomes complex. Therefore a new approach is implemented to overcome the issues related to the execution time, namely Field Programmable Gate Array (FPGA) processors are suggested in the present market. Moreover the programming is done using very high speed hardware descriptive language (VHDL)

Simulation and Analysis of different CMOS Full Adders for Delay Optimisation

2021 ◽  
Vol 9 (9) ◽  
pp. 66-70
Author(s):  
Nakul C. Kubsad
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Digital Signal ◽  
Full Adder ◽  
Digital Signal Processors ◽  
Transmission Gate ◽  
Logical Operations ◽  
Recent Advancement ◽  
Voltage Swing ◽  
Signal Processors

Abstract: Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.

High Speed Vedic Multiplier for Digital Signal Processors

2009 ◽  
Vol 55 (6) ◽  
pp. 282 ◽  
Author(s):  
Ramesh Pushpangadan ◽  
Vineeth Sukumaran ◽  
Rino Innocent ◽  
Dinesh Sasikumar ◽  
Vaisak Sundar
Keyword(s):  
High Speed ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Vedic Multiplier ◽  
Signal Processors

scholarly journals Enhanced and Efficient Carry Select Adder with Minimal Delay

2021 ◽  
Author(s):  
G. Srividhya ◽  
T. Sivasakthi ◽  
R. Srivarshini ◽  
P. Varshaa ◽  
S. Vijayalakshmi
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Digital Signal ◽  
Propagation Delay ◽  
Digital Signal Processors ◽  
Digital World ◽  
Carry Select Adder ◽  
Image Processors ◽  
Improved Model ◽  
Signal Processors

In today’s digital world, Arithmetic computations have been evolved as a core factor in digital signal processors, micro-controllers, and systems using arithmetic and logical operations such as adders, multipliers, image processors, and signal processors. One of the elements that play an important role in performing arithmetic calculations is an adder. Among many adders, the Carry Select Adder produces less propagation delay. However, there may be an increased delay, power consumption, and area required in the case of a normal Carry Select Adder. To overcome the mentioned drawbacks, an improved model of Carry Select Adder has been designed that uses Binary to Excess – 1 Converter. Instead of using multiple blocks of Ripple Carry Adders (RCAs), it is efficient and effective if one of the blocks is replaced with Binary to Excess – 1 Converter. As a result, we can achieve a high speed adder with minimal delay, minimal power, and reduced area.

scholarly journals Digital signal processing designing for FPGA architectures

2007 ◽  
Vol 20 (3) ◽  
pp. 437-459 ◽  
Author(s):  
Mariusz Rawski ◽  
Bogdan Falkowski ◽  
Tadeusz Łuba
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Distributed Arithmetic ◽  
Embedded Blocks ◽  
Signal Processing Algorithms ◽  
Signal Processors ◽  
High Degree ◽  
Very High

This paper presents the discussion on efficiency of different implementation methodologies of DSP algorithms targeted for modern FPGA architectures. Modern programmable structures are equipped with specialized DSP embedded blocks that allow implementing digital signal processing algorithms with use of the methodology known from digital signal processors. On the first place however, programmable architectures give the designer the possibility to increase efficiency of designed system by exploitation of parallelism of implemented algorithms. Moreover, it is possible to apply special techniques such as distributed arithmetic (DA) that will boost the performance of designed processing systems. Additionally, application of the functional decomposition based methods, known to be best suited for FPGA structures allows utilizing possibilities of programmable technology in very high degree. The paper presents results of comparison of different design approaches in this area.

BLOCK FLOATING POINT FFT IMPLEMENTATION FOR DMT xDSL SYSTEMS

2004 ◽  
Vol 13 (05) ◽  
pp. 1147-1164
Author(s):  
Th. ZAHARIADIS ◽  
S. APOSTOLACOS ◽  
I. GRAMMATIKAKIS ◽  
D. MEXIS ◽  
N. ZERVOS ◽  
...  
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Digital Signal ◽  
Floating Point ◽  
Digital Subscriber Line ◽  
Discrete Multitone ◽  
Field Programmable ◽  
Signal Processing Algorithms ◽  
Programmable Gate Arrays ◽  
Signal Processors

The development of multiple Discrete Multitone (DMT) Digital Subscriber Line (DSL) flavors on a single platform can benefit considerably by a programmable architecture, which feature Digital Signal Processors (DSP) and Field Programmable Gate Arrays (FPGA), especially when fast prototyping is targeted. However, the flexibility assumed to be offered by algorithmic partitioning does not automatically and proportionally simplify the digital signal processing algorithms, unless the effects of overflow/saturation in intermediate processing stages are carefully studied. The effects of overflow/saturation in intermediate stages is very critical throughout the design process, since the operations involved are nonlinear in nature and affect the most significant bits of the computational process. This paper presents an efficient soft-core implementation of a Block Floating Point FFT (BLFP) algorithm, designed for a Very high-speed DSL (VDSL) DMT systems and for the full variety of other xDSL DMT flavors, as the latter demand an extended dynamic range to achieve performance that may otherwise be only warranted by costly floating-point chip implementations.

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