scholarly journals Implementation of a high speed four transmitter space-time encoder using field programmable gate array and parallel digital signal processors

2006 ◽  
Author(s):  
P.J. Green ◽  
D.P. Taylor
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Digital Signal ◽  
Space Time ◽  
Digital Signal Processors ◽  
Field Programmable ◽  
Gate Array ◽  
Signal Processors

scholarly journals Space-time trellis codes: Field programmable gate array approach

2020 ◽  
Vol 9 (3) ◽  
pp. 213
Author(s):  
Mallikarjuna Gowda C. P. ◽  
Raju Hajare
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Low Cost ◽  
Digital Signal ◽  
Space Time ◽  
Trellis Codes ◽  
Software Environment ◽  
High Data ◽  
Field Programmable ◽  
Gate Array

This paper presents an implementation of Space-time Trellis Codes for 4-state on FPGA. To reach the very high data rates provided in STTC, a lot of expensive high-speed Digital Signal Processors (DSPs) should be employed for the real time applications, while it might not be affordable. This fact has motivated in designing dedicated hardware implementations using Field Programmable Gate Array (FPGA) with low cost and power consumption. The hardware device XC3S400, family Xilinx Spartan-3, and package PQ208 are used in this project, in which the STTC encoder and decoder utilizes maximum 10% and 22% as that of available device capacity respectively. The design has been simulated and synthesized successfully in Xilinx integrated software environment.

scholarly journals FPGA Based Vector Control of Induction Motor

2020 ◽  
Vol 9 (4) ◽  
pp. 572-577
Keyword(s):  
Induction Motor ◽  
High Speed ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Electronic Industry ◽  
New Approach ◽  
The Past ◽  
Field Programmable ◽  
Signal Processors ◽  
Very High

To get the desired response of the sensor less Vector controlled Induction Motor (SVC-IM) by the experimental setup, the controller implementation for the generation of the PWM signals is the key role. It is possible with the rapid growth of electronic industry such as high speed digital signal processors (DSPs) with micro controllers available in the present market. In the past DSP technologies were used to realize the several SVC-IM schemes, i.e. KF, PI, GA and PSO respectively. However, it creates issues related to the time delay and execution of the PWM signals, etc., as a results system becomes complex. Therefore a new approach is implemented to overcome the issues related to the execution time, namely Field Programmable Gate Array (FPGA) processors are suggested in the present market. Moreover the programming is done using very high speed hardware descriptive language (VHDL)

High Speed FPGA Based 128-bit Advance Encryption Standard (AES)

2021 ◽  
Vol 11 ◽  
Author(s):  
Ibrahem M. T. Hamidi ◽  
Farah S. H. Al-aassi
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Design Tool ◽  
Advanced Encryption Standard ◽  
Clock Frequency ◽  
Advance Encryption Standard ◽  
Field Programmable ◽  
Internal Component ◽  
Gate Array

Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.

Simulation and Analysis of different CMOS Full Adders for Delay Optimisation

2021 ◽  
Vol 9 (9) ◽  
pp. 66-70
Author(s):  
Nakul C. Kubsad
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Digital Signal ◽  
Full Adder ◽  
Digital Signal Processors ◽  
Transmission Gate ◽  
Logical Operations ◽  
Recent Advancement ◽  
Voltage Swing ◽  
Signal Processors

Abstract: Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.

scholarly journals Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

2019 ◽  
Vol 29 (09) ◽  
pp. 2050136
Author(s):  
Yuuki Tanaka ◽  
Yuuki Suzuki ◽  
Shugang Wei
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Number System ◽  
Logic Circuit ◽  
Fpga Implementation ◽  
Number Representation ◽  
Representation System ◽  
Representation Systems ◽  
Field Programmable ◽  
Gate Array

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

A very-high-speed field-programmable gate array using metal-to-metal antifuse programmable elements

1992 ◽  
Vol 23 (7) ◽  
pp. 561-568 ◽  
Author(s):  
J. Birkner ◽  
A. Chan ◽  
H.T. Chua ◽  
A. Chao ◽  
K. Gordon ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Field Programmable ◽  
Gate Array ◽  
Very High
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