scholarly journals Advanced Improvement in Speed of Operation of 3-Stage CMOS Ring Oscillator Clock Generation using CPG

The Ring oscillator is a member of time delay Oscillators. In this Ring oscillator it uses odd number of inverters and has a gain greater than one. In normal Ring Oscillator architecture the performance is very low due to power gating mechanism. By using CPG technique the performance is increased and also utilizes low power for operation. This Ring oscillator by using CPG technique is affected by pressure and temperature variations. By using 3-stage CMOS ring oscillator the efficiency and performance is increased. In CMOS Ring oscillator power supervision (PS) and efficiency is increased. Most of the architecture is planned for cut back the ability within the IPs to provide power gating, with the task of falling system level control gating. In this CMOS Ring oscillator the output of each NOT gate is given to next stage in order to improve the system latency. For CMOS Ring oscillator, there is no output is given to system, but Reset pulse will drive the entire architecture. In CPG power of the device will change in cyclic manner, device will be ON and OFF over small duration of time. By this proposed method over all power consumption and speed of operation is increased

2011 ◽  
Vol 134 (1) ◽  
Author(s):  
Andreas Peters ◽  
Zoltán S. Spakovszky

Due to their inherent noise challenge and potential for significant reductions in fuel burn, counter-rotating propfans (CRPs) are currently being investigated as potential alternatives to high-bypass turbofan engines. This paper introduces an integrated noise and performance assessment methodology for advanced propfan powered aircraft configurations. The approach is based on first principles and combines a coupled aircraft and propulsion system mission and performance analysis tool with 3D unsteady, full-wheel CRP computational fluid dynamics computations and aeroacoustic simulations. Special emphasis is put on computing CRP noise due to interaction tones. The method is capable of dealing with parametric studies and exploring noise reduction technologies. An aircraft performance, weight and balance, and mission analysis was first conducted on a candidate CRP powered aircraft configuration. Guided by data available in the literature, a detailed aerodynamic design of a pusher CRP was carried out. Full-wheel unsteady 3D Reynolds-averaged Navier-Stokes (RANS) simulations were then used to determine the time varying blade surface pressures and unsteady flow features necessary to define the acoustic source terms. A frequency domain approach based on Goldstein’s formulation of the acoustic analogy for moving media and Hanson’s single rotor noise method was extended to counter-rotating configurations. The far field noise predictions were compared to measured data of a similar CRP configuration and demonstrated good agreement between the computed and measured interaction tones. The underlying noise mechanisms have previously been described in literature but, to the authors’ knowledge, this is the first time that the individual contributions of front-rotor wake interaction, aft-rotor upstream influence, hub-endwall secondary flows, and front-rotor tip-vortices to interaction tone noise are dissected and quantified. Based on this investigation, the CRP was redesigned for reduced noise incorporating a clipped rear-rotor and increased rotor-rotor spacing to reduce upstream influence, tip-vortex, and wake interaction effects. Maintaining the thrust and propulsive efficiency at takeoff conditions, the noise was calculated for both designs. At the interaction tone frequencies, the redesigned CRP demonstrated an average reduction of 7.25 dB in mean sound pressure level computed over the forward and aft polar angle arcs. On the engine/aircraft system level, the redesigned CRP demonstrated a reduction of 9.2 dB in effective perceived noise (EPNdB) and 8.6 EPNdB at the Federal Aviation Regulations (FAR) 36 flyover and sideline observer locations, respectively. The results suggest that advanced open rotor designs can possibly meet Stage 4 noise requirements.


2010 ◽  
Vol 20 (02) ◽  
pp. 103-121 ◽  
Author(s):  
MOSTAFA I. SOLIMAN ◽  
ABDULMAJID F. Al-JUNAID

Technological advances in IC manufacturing provide us with the capability to integrate more and more functionality into a single chip. Today's modern processors have nearly one billion transistors on a single chip. With the increasing complexity of today's system, the designs have to be modeled at a high-level of abstraction before partitioning into hardware and software components for final implementation. This paper explains in detail the implementation and performance evaluation of a matrix processor called Mat-Core with SystemC (system level modeling language). Mat-Core is a research processor aiming at exploiting the increasingly number of transistors per IC to improve the performance of a wide range of applications. It extends a general-purpose scalar processor with a matrix unit. To hide memory latency, the extended matrix unit is decoupled into two components: address generation and data computation, which communicate through data queues. Like vector architectures, the data computation unit is organized in parallel lanes. However, on parallel lanes, Mat-Core can execute matrix-scalar, matrix-vector, and matrix-matrix instructions in addition to vector-scalar and vector-vector instructions. For controlling the execution of vector/matrix instructions on the matrix core, this paper extends the well known scoreboard technique. Furthermore, the performance of Mat-Core is evaluated on vector and matrix kernels. Our results show that the performance of four lanes Mat-Core with matrix registers of size 4 × 4 or 16 elements each, queues size of 10, start up time of 6 clock cycles, and memory latency of 10 clock cycles is about 0.94, 1.3, 2.3, 1.6, 2.3, and 5.5 FLOPs per clock cycle; achieved on scalar-vector multiplication, SAXPY, Givens, rank-1 update, vector-matrix multiplication, and matrix-matrix multiplication, respectively.


Author(s):  
Sudhakar Y. Reddy

Abstract This paper describes HIDER, a methodology that enables detailed simulation models to be used during the early stages of system design. HIDER uses a machine learning approach to form abstract models from the detailed models. The abstract models are used for multiple-objective optimization to obtain sets of non-dominated designs. The tradeoffs between design and performance attributes in the non-dominated sets are used to interactively refine the design space. A prototype design tool has been developed to assist the designer in easily forming abstract models, flexibly defining optimization problems, and interactively exploring and refining the design space. To demonstrate the practical applicability of this approach, the paper presents results from the application of HIDER to the system-level design of a wheel loader. In this demonstration, complex simulation models for cycle time evaluation and stability analysis are used together for early-stage exploration of design space.


2002 ◽  
Vol 124 (3) ◽  
pp. 441-450 ◽  
Author(s):  
R. Scott Erwin ◽  
Karl Schrader ◽  
Ruth L. Moser ◽  
Steven F. Griffin

This paper presents the development, design, and implementation of a precision control system for a large, sparse-aperture space-deployable telescope testbed. Aspects of the testbed and laboratory environment relevant to nanometer-level control and performance objectives are provided. There are four main objectives of the control system: 1) reduction of natural resonances of the supporting structure, 2) rejection of tonal disturbances, 3) tip, tilt, and piston set-point tracking for optical surfaces, and 4) reduction in settling time of optical surfaces after an impulsive slew-type disturbance. The development of a three-input, three-output, high-bandwidth structural control system for the testbed is presented, and experimental data demonstrating that all objectives were attained is provided. The paper concludes with a discussion of the results and a description of research issues remaining to be addressed.


Sign in / Sign up

Export Citation Format

Share Document