scholarly journals Design and Implementation of Pipelined AES Encryption System using FPGA

2020 ◽  
Vol 8 (5) ◽  
pp. 2565-2571
Keyword(s):  
Data Transmission ◽  
Data Encryption ◽  
Advanced Encryption Standard ◽  
Sensitive Data ◽  
Field Programmable ◽  
Speed Up ◽  
Encryption Algorithms ◽  
A New Technique ◽  
Rijndael Algorithm ◽  
Normal Processing

Nowadays, the data encryption became very important because of the usage of the data transmission in all the filed. The Advanced Encryption Standard (AES) that known as Rijndael algorithm is one of the most common encryption algorithms. The AES consists of 9 rounds in addition to the initial and final rounds that makes the AES consumes much time for encrypting the data. Of course the time consumption is considered one of the problems that face the information security. The more time the encryption system consumes to encrypt the data, the more chances increase for the hackers to break into the system. In this work, we find a new technique that can be used to increase the performance speed of the advanced encryption standard. The proposed algorithm methodology depends on the pipelined processing method for the processing time reduction. The paper includes a discussion of the design, the analysis and the implementation using Field Programmable Gate Array (FPGA) of the pipelined method to reduce the consumed numbers of clocks and speed up the processes. The AES is used to protect information and encrypt sensitive data and used in satellites, missiles, military application and other critical application. The paper describes the AES encryption system algorithm and the implementation of both the normal processing and the pipelined processing, and finally a comparison between the two algorithms.

scholarly journals Evaluating Encryption Algorithms for Sensitive Data Using Different Storage Devices

2020 ◽  
Vol 2020 ◽  
pp. 1-9 ◽  
Author(s):  
Bahman A. Sassani (Sarrafpour) ◽  
Mohammed Alkorbi ◽  
Noreen Jamil ◽  
M. Asif Naeem ◽  
Farhaan Mirza
Keyword(s):  
Flash Memory ◽  
Full Range ◽  
Data Encryption ◽  
Storage Device ◽  
Sensitive Data ◽  
Hard Drives ◽  
Storage Devices ◽  
Aes Algorithm ◽  
Encryption Algorithms ◽  
Storage Encryption

Sensitive data need to be protected from being stolen and read by unauthorized persons regardless of whether the data are stored in hard drives, flash memory, laptops, desktops, and other storage devices. In an enterprise environment where sensitive data is stored on storage devices, such as financial or military data, encryption is used in the storage device to ensure data confidentiality. Nowadays, the SSD-based NAND storage devices are favored over HDD and SSHD to store data because they offer increased performance and reduced access latency to the client. In this paper, the performance of different symmetric encryption algorithms is evaluated on HDD, SSHD, and SSD-based NAND MLC flash memory using two different storage encryption software. Based on the experiments we carried out, Advanced Encryption Standard (AES) algorithm on HDD outperforms Serpent and Twofish algorithms in terms of random read speed and write speed (both sequentially and randomly), whereas Twofish algorithm is slightly faster than AES in sequential reading on SSHD and SSD-based NAND MLC flash memory. By conducting full range of evaluative tests across HDD, SSHD, and SSD, our experimental results can give better idea for the storage consumers to determine which kind of storage device and encryption algorithm is suitable for their purposes. This will give them an opportunity to continuously achieve the best performance of the storage device and secure their sensitive data.

scholarly journals Comparison of AES and DES Algorithms Implemented on Virtex-6 FPGA and Microblaze Soft Core Processor

2018 ◽  
Vol 8 (5) ◽  
pp. 3544
Author(s):  
G. Renuka ◽  
V. Usha Shree ◽  
P. Chandra Sekhar Reddy
Keyword(s):  
Dominant Role ◽  
Data Encryption ◽  
Soft Core ◽  
Advanced Encryption Standard ◽  
Description Language ◽  
Important Data ◽  
Data Encryption Standard ◽  
Software Implementations ◽  
Hardware Description ◽  
Encryption Algorithms

Encryption algorithms play a dominant role in preventing unauthorized access to important data. This paper focus on the implementations of Data Encryption Standard (DES) and Advanced Encryption Standard (AES) algorithms on Microblaze soft core Processor and also their implementations on XC6VLX240t FPGA using Verilog Hardware Description language. This paper also gives a comparison of the issues related to the hardware and software implementations of the two cryptographic algorithms.

scholarly journals Analysis of Encryption Techniques to Enhance Secure Data Transmission

2018 ◽  
Vol 7 (09) ◽  
pp. 24311-24318
Author(s):  
Rajesh Kannan ◽  
Dr. R. Mala
Keyword(s):  
Access Control ◽  
Data Transmission ◽  
Data Encryption ◽  
Unstructured Data ◽  
Huge Amount ◽  
Security Breaches ◽  
Private Data ◽  
Confidential Data ◽  
Secure Data Transmission ◽  
Encryption Algorithms

with the rapid increase of technology, the data stored and transmitted among the client and server has been increased tremendously. In order to provide high security for the confidential data, there is a need for proper encryption techniques that are to be followed by the concerns. This paper presents an analysis of the various encryption algorithms and their performance on handling the private data with authentication, access control, secure configuration and data encryption. Document oriented databases such as MongoDB, Cassandra, CouchDB, Redis and Hypertable are compared on the basis of their security aspects since they manipulate the huge amount of unstructured data in their databases. It is proposed that each database has its own security breaches and emphasises the need for proper encryption methods to secure the data stored in them. 

scholarly journals Cloud based Secure Storage of Files using Hybrid Cryptography and Image Steganography

2020 ◽  
Vol 8 (6) ◽  
pp. 665-667
Keyword(s):  
Data Encryption ◽  
Image Steganography ◽  
Advanced Encryption Standard ◽  
Sensitive Information ◽  
Least Significant Bit ◽  
Data Encryption Standard ◽  
Secure Storage ◽  
Symmetric Key ◽  
Encryption Algorithms ◽  
High Level

Cloud Computing has made it possible to provide individuals as well as organizations with a utility that is costeffective. It empowers businesses by delivering these services using the internet. Files can be shared through the cloud. These files may contain sensitive information that needs to be kept hidden from anonymous users. This is done using cryptographic algorithms. High level of security can be provided using hybrid cryptography to encrypt the data. Advanced Encryption Standard (AES) and Triple Data Encryption Standard (3DES) are the symmetric key encryption algorithms used to secure. An asymmetric key encryption algorithm, Rivest-Shamir-Adleman (RSA) helps in providing a hybrid cryptography model. The security of the key generated can be further enhanced using image steganography method Least Significant Bit (LSB). These issues regarding the security and its challenges will be addressed in this paper and also analyse the measures to handle it.

scholarly journals A Dynamic Light-Weight Symmetric Encryption Algorithm for Secure Data Transmission via BLE Beacons

2021 ◽  
Vol 11 (1) ◽  
pp. 2
Author(s):  
Sam Banani ◽  
Surapa Thiemjarus ◽  
Kitti Wongthavarawat ◽  
Nattapong Ounanong
Keyword(s):  
Data Transmission ◽  
Data Encryption ◽  
Sensor Nodes ◽  
Encryption Algorithm ◽  
Light Weight ◽  
Symmetric Encryption ◽  
Avalanche Effect ◽  
Secure Data ◽  
Secure Data Transmission ◽  
Encryption Algorithms

Pervasive sensing with Body Sensor Networks (BSNs) is a promising technology for continuous health monitoring. Since the sensor nodes are resource-limited, on-node processing and advertisement of digested information via BLE beacon is a promising technique that can enable a node gateway to communicate with more sensor nodes and extend the sensor node’s lifetime before requiring recharging. This study proposes a Dynamic Light-weight Symmetric (DLS) encryption algorithm designed and developed to address the challenges in data protection and real-time secure data transmission via message advertisement. The algorithm uses a unique temporal encryption key to encrypt each transmitting packet with a simple function such as XOR. With small additional overhead on computational resources, DLS can significantly enhance security over existing baseline encryption algorithms. To evaluate its performance, the algorithm was utilized on beacon data encryption over advertising channels. The experiments demonstrated the use of the DLS encryption algorithm on top of various light-weight symmetric encryption algorithms (i.e., TEA, XTEA, PRESENT) and a MD5 hash function. The experimental results show that DLS can achieve acceptable results for avalanche effect, key sensitivity, and randomness in ciphertexts with a marginal increase in the resource usage. The proposed DLS encryption algorithm is suitable for implementation at the application layer, is light and energy efficient, reduces/removes the need for secret key exchange between sensor nodes and the server, is applicable to dynamic message size, and also protects against attacks such as known plaintext attack, brute-force attack, replaying attack, and differential attack.

VLSI Implementation of Low Power High Speed ECC Processor Using Versatile Bit Serial Multiplier

2017 ◽  
Vol 26 (07) ◽  
pp. 1750114 ◽  
Author(s):  
M. Srinivasan ◽  
G. M. Tamilselvan
Keyword(s):  
Elliptic Curve Cryptography ◽  
High Speed ◽  
Advanced Encryption Standard ◽  
Power Performance ◽  
Time Performance ◽  
Unit Operations ◽  
Traditional Design ◽  
Field Programmable ◽  
Encryption Algorithms ◽  
Bit Serial

In this paper, an area competent field-programmable gate array (FPGA) execution scheme of elliptic curve cryptography (ECC) is depicted. There are numerous limitations in traditional encryption algorithms such us Rivest Shamir Adleman (RSA), Advanced Encryption Standard (AES) in respect of security, power, and resources at the real-time performance. The ECC is mounting as an imperative cryptography, and gives you an idea about a promise to be the substitute of RSA. In this paper, ECC processor architecture over Galois Fields (GFs) with the multitalented bit serial multiplier is depicted which accomplishes the greatest area and power performance over traditional digit-serial multiplier. In addition, the vigilant scheduling operation was employed to diminish the involvedness of logic unit operations in ECC processor. The anticipated architecture is executed on vertex4 FPGA expertise in Xilinx software. We demonstrate that results perk up the performance of the enhanced design by contrasting with the traditional design.

scholarly journals Secure Data Transmission using Goldbach Codes and RSA Algorithm

2019 ◽  
Vol 8 (4) ◽  
pp. 5-8
Keyword(s):  
Data Compression ◽  
Data Transmission ◽  
Data Encryption ◽  
Compression Algorithms ◽  
Rsa Algorithm ◽  
Code Algorithm ◽  
Secure Data ◽  
Secure Data Transmission ◽  
Encryption Algorithms

Information transmitted through the insecure network need to be secured by using different methods. There are several cryptographic methods to ensure secure data transmission. The compression algorithms are used to compress the information, then on the compressed information encryption algorithms can be applied so as to reduce the time of encryption. There are several data compression algorithms available to compress the data. Our proposed scheme is a combination of Goldbach Code Algorithm for data compression, and the RSA algorithm for data encryption.

scholarly journals Advanced Encryption Standard for Data Encryption using EDK Environment in FPGA

2019 ◽  
Vol 8 (4) ◽  
pp. 11969-11972
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Data Encryption ◽  
Advanced Encryption Standard ◽  
Gate Arrays ◽  
Aes Algorithm ◽  
Encryption And Decryption ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Efficient Processing

now a day’s VLSI is developing technology as predicted by Moors law which is drastically increasing as per demand one of that is data security for efficient processing so, data encryption and decryption are major play in security for this an advanced encryption standard is there which uses reconfigurable hardware process in this paper field programmable gate arrays (FPGAs) kit of Xilinx based platform in which spartan3E EDK kit is used. Here we analyze the speed of AES algorithm by using this EDK environment where obvious high speed is considerable and with power consumption and throughput exemptions. With micro blaze soft core processer we implement our algorithm of AES by using c coding we configure the hardware structure. EDK tool with one round operation is done and both area utilization and throughput are observed as we are familiar that when area reduces power consumption also reduces.

High Speed FPGA Based 128-bit Advance Encryption Standard (AES)

2021 ◽  
Vol 11 ◽  
Author(s):  
Ibrahem M. T. Hamidi ◽  
Farah S. H. Al-aassi
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Design Tool ◽  
Advanced Encryption Standard ◽  
Clock Frequency ◽  
Advance Encryption Standard ◽  
Field Programmable ◽  
Internal Component ◽  
Gate Array

Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.

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