VLSI Implementation of Low Power High Speed ECC Processor Using Versatile Bit Serial Multiplier

2017 ◽  
Vol 26 (07) ◽  
pp. 1750114 ◽  
Author(s):  
M. Srinivasan ◽  
G. M. Tamilselvan
Keyword(s):  
Elliptic Curve Cryptography ◽  
High Speed ◽  
Advanced Encryption Standard ◽  
Power Performance ◽  
Time Performance ◽  
Unit Operations ◽  
Traditional Design ◽  
Field Programmable ◽  
Encryption Algorithms ◽  
Bit Serial

In this paper, an area competent field-programmable gate array (FPGA) execution scheme of elliptic curve cryptography (ECC) is depicted. There are numerous limitations in traditional encryption algorithms such us Rivest Shamir Adleman (RSA), Advanced Encryption Standard (AES) in respect of security, power, and resources at the real-time performance. The ECC is mounting as an imperative cryptography, and gives you an idea about a promise to be the substitute of RSA. In this paper, ECC processor architecture over Galois Fields (GFs) with the multitalented bit serial multiplier is depicted which accomplishes the greatest area and power performance over traditional digit-serial multiplier. In addition, the vigilant scheduling operation was employed to diminish the involvedness of logic unit operations in ECC processor. The anticipated architecture is executed on vertex4 FPGA expertise in Xilinx software. We demonstrate that results perk up the performance of the enhanced design by contrasting with the traditional design.

High Speed FPGA Based 128-bit Advance Encryption Standard (AES)

2021 ◽  
Vol 11 ◽  
Author(s):  
Ibrahem M. T. Hamidi ◽  
Farah S. H. Al-aassi
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Design Tool ◽  
Advanced Encryption Standard ◽  
Clock Frequency ◽  
Advance Encryption Standard ◽  
Field Programmable ◽  
Internal Component ◽  
Gate Array

Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.

Architecture of ASIP Crypto-Processor for Dynamic Runtime Security Applications

2016 ◽  
Vol 4 (2) ◽  
pp. 412
Author(s):  
Mahaba Saad ◽  
Khalid Youssef ◽  
Mohamed Tarek ◽  
Hala Abdel-Kader
Keyword(s):  
Quantitative Analysis ◽  
High Speed ◽  
Reference Model ◽  
Power Performance ◽  
Security Applications ◽  
Logical Operations ◽  
Symmetric Key ◽  
Encryption Algorithms ◽  
Security Operations ◽  
The Masses

<p>Nowadays, demands of data security are increasing, especially after introduction of wireless communications to the masses. Cryptographic algorithms are mainly used to obtain confidentiality and integrity of data in communication. There are a variety of encryption algorithms have been developed. This paper provides quantitative analysis and comparison of some symmetric key cryptographic ciphers (DES, 3DES, AES, Blowfish, RC5, and RC6).  The quantitative analysis approach is a step towards optimizing the security operations for an efficient next generation family of network processors with enhanced speed and power performance. A framework will be proposed as a reference model for quantitative analysis of security algorithm mathematical and logical operations. This paper also provides a dynamic crypto processor used for selected symmetric key cryptographic ciphers   and  provides an implementation of 16bit cryptographic processor that performs logical operations and arithmetic operations like rotate shift left, modular addition 2^16, S_box operation, and key expansion operation  on spartan6 lower power, xc6slx150L-1lfgg676 FPGA. Simulation results show that developed processor working with high Speed, low power, and low delay time. </p>

scholarly journals Design and Implementation of Pipelined AES Encryption System using FPGA

2020 ◽  
Vol 8 (5) ◽  
pp. 2565-2571
Keyword(s):  
Data Transmission ◽  
Data Encryption ◽  
Advanced Encryption Standard ◽  
Sensitive Data ◽  
Field Programmable ◽  
Speed Up ◽  
Encryption Algorithms ◽  
A New Technique ◽  
Rijndael Algorithm ◽  
Normal Processing

Nowadays, the data encryption became very important because of the usage of the data transmission in all the filed. The Advanced Encryption Standard (AES) that known as Rijndael algorithm is one of the most common encryption algorithms. The AES consists of 9 rounds in addition to the initial and final rounds that makes the AES consumes much time for encrypting the data. Of course the time consumption is considered one of the problems that face the information security. The more time the encryption system consumes to encrypt the data, the more chances increase for the hackers to break into the system. In this work, we find a new technique that can be used to increase the performance speed of the advanced encryption standard. The proposed algorithm methodology depends on the pipelined processing method for the processing time reduction. The paper includes a discussion of the design, the analysis and the implementation using Field Programmable Gate Array (FPGA) of the pipelined method to reduce the consumed numbers of clocks and speed up the processes. The AES is used to protect information and encrypt sensitive data and used in satellites, missiles, military application and other critical application. The paper describes the AES encryption system algorithm and the implementation of both the normal processing and the pipelined processing, and finally a comparison between the two algorithms.

Improved Synthesis of Generalized Parallel Counters on FPGAs Using Only LUTs

2017 ◽  
Vol 27 (01) ◽  
pp. 1850002
Author(s):  
Burhan Khurshid
Keyword(s):  
High Speed ◽  
Field Programmable Gate Arrays ◽  
Prior Work ◽  
Power Performance ◽  
Output Node ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

Generalized parallel counters (GPCs) are frequently used to construct high speed compressor trees on field programmable gate arrays (FPGAs). The introduction of fast carry-chain in FPGAs has greatly improved the performance of these elements. Evidently, a large number of GPCs have been proposed in literature that use a combination of look-up tables (LUTs) and carry-chains. In this paper, we take an alternate approach and try to eliminate the carry-chain from the GPC structure. We present a heuristic that aims at synthesizing GPCs on FPGAS using only the general LUT fabric. The resultant GPCs are then easily pipelined by placing registers at the output node of each LUT. We have used our heuristic on various GPCs reported in prior work. Our heuristic successfully eliminates the carry-chain from the GPC structure with an increase in LUT count in some GPCs. Experimentation using Xilinx FPGAs shows that filter systems constructed using our GPCs show an improvement in speed and power performance and a comparable area performance.

scholarly journals Advanced Encryption Standard for Data Encryption using EDK Environment in FPGA

2019 ◽  
Vol 8 (4) ◽  
pp. 11969-11972
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Data Encryption ◽  
Advanced Encryption Standard ◽  
Gate Arrays ◽  
Aes Algorithm ◽  
Encryption And Decryption ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Efficient Processing

now a day’s VLSI is developing technology as predicted by Moors law which is drastically increasing as per demand one of that is data security for efficient processing so, data encryption and decryption are major play in security for this an advanced encryption standard is there which uses reconfigurable hardware process in this paper field programmable gate arrays (FPGAs) kit of Xilinx based platform in which spartan3E EDK kit is used. Here we analyze the speed of AES algorithm by using this EDK environment where obvious high speed is considerable and with power consumption and throughput exemptions. With micro blaze soft core processer we implement our algorithm of AES by using c coding we configure the hardware structure. EDK tool with one round operation is done and both area utilization and throughput are observed as we are familiar that when area reduces power consumption also reduces.

Accelerating laser processes with a smart two-dimensional polygon mirror scanner for ultra-fast beam deflection

2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Florian Roessler ◽  
André Streek
Keyword(s):  
Energy Distribution ◽  
Real Time ◽  
Laser Processing ◽  
High Speed ◽  
Beam Deflection ◽  
Two Dimensional ◽  
Heat Accumulation ◽  
Field Programmable ◽  
Drill Holes ◽  
Average Laser

Abstract In laser processing, the possible throughput is directly scaling with the available average laser power. To avoid unwanted thermal damage due to high pulse energy or heat accumulation during MHz-repetition rates, energy distribution over the workpiece is required. Polygon mirror scanners enable high deflection speeds and thus, a proper energy distribution within a short processing time. The requirements of laser micro processing with up to 10 kW average laser powers and high scan speeds up to 1000 m/s result in a 30 mm aperture two-dimensional polygon mirror scanner with a patented low-distortion mirror configuration. In combination with a field programmable gate array-based real-time logic, position-true high-accuracy laser switching is enabled for 2D, 2.5D, or 3D laser processing capable to drill holes in multi-pass ablation or engraving. A special developed real-time shifter module within the high-speed logic allows, in combination with external axis, the material processing on the fly and hence, processing of workpieces much larger than the scan field.

Based on FPGA Intelligent Physiological Parameters Acquisition

2013 ◽  
Vol 344 ◽  
pp. 107-110
Author(s):  
Shun Ren Hu ◽  
Ya Chen Gan ◽  
Ming Bao ◽  
Jing Wei Wang
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Physiological Parameters ◽  
Sensor Data ◽  
Low Power Consumption ◽  
Physiological Signal ◽  
Pulse Sensor ◽  
Monitoring Applications ◽  
Field Programmable ◽  
Design Ideas

For the physiological signal monitoring applications, as a micro-controller based on field programmable gate array (FPGA) physiological parameters intelligent acquisition system is given, which has the advantages of low cost, high speed, low power consumption. FPGA is responsible for the completion of pulse sensor, the temperature sensor, acceleration sensor data acquisition and serial output and so on. Focuses on the design ideas and architecture of the various subsystems of the whole system, gives the internal FPGA circuit diagram of the entire system. The whole system is easy to implement and has a very good promotional value.

AlGaN/GaN HEMTs: RECENT DEVELOPMENTS AND FUTURE DIRECTIONS

2008 ◽  
Vol 18 (04) ◽  
pp. 913-922 ◽  
Author(s):  
SIDDHARTH RAJAN ◽  
UMESH K. MISHRA ◽  
TOMÁS PALACIOS
Keyword(s):  
Field Effect ◽  
High Speed ◽  
Digital Circuits ◽  
Field Effect Transistors ◽  
Rf Power ◽  
Power Performance ◽  
Future Directions ◽  
Recent Developments ◽  
Gan Hemts ◽  
State Of Art

This paper provides an overview of recent work and future directions in Gallium Nitride transistor research. We discuss the present status of Ga -polar AlGaN / GaN HEMTs and the innovations that have led to record RF power performance. We describe the development of N -polar AlGaN / GaN HEMTs with microwave power performance comparable with state-of-art Ga -polar AlGaN / GaN HEMTs. Finally we will discuss how GaN -based field effect transistors could be promising for a less obvious application: low-power high-speed digital circuits.

scholarly journals AC_ICAP: A Flexible High Speed ICAP Controller

2015 ◽  
Vol 2015 ◽  
pp. 1-15 ◽  
Author(s):  
Luis Andres Cardona ◽  
Carles Ferrer
Keyword(s):  
High Speed ◽  
Access Port ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Speed Up ◽  
Run Time ◽  
Ip Cores ◽  
Similar Solutions ◽  
Internal Configuration ◽  
Run Time Reconfiguration

The Internal Configuration Access Port (ICAP) is the core component of any dynamic partial reconfigurable system implemented in Xilinx SRAM-based Field Programmable Gate Arrays (FPGAs). We developed a new high speed ICAP controller, named AC_ICAP, completely implemented in hardware. In addition to similar solutions to accelerate the management of partial bitstreams and frames, AC_ICAP also supports run-time reconfiguration of LUTs without requiring precomputed partial bitstreams. This last characteristic was possible by performing reverse engineering on the bitstream. Besides, we adapted this hardware-based solution to provide IP cores accessible from the MicroBlaze processor. To this end, the controller was extended and three versions were implemented to evaluate its performance when connected to Peripheral Local Bus (PLB), Fast Simplex Link (FSL), and AXI interfaces of the processor. In consequence, the controller can exploit the flexibility that the processor offers but taking advantage of the hardware speed-up. It was implemented in both Virtex-5 and Kintex7 FPGAs. Results of reconfiguration time showed that run-time reconfiguration of single LUTs in Virtex-5 devices was performed in less than 5 μs which implies a speed-up of more than 380x compared to the Xilinx XPS_HWICAP controller.

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