scholarly journals Implementation of AMBA Based AHB2APB Bridge

2020 ◽  
Vol 8 (6) ◽  
pp. 1033-1037
Keyword(s):  
Embedded System ◽  
High Speed ◽  
High Performance ◽  
Data Loss ◽  
Verilog Hdl ◽  
Main Target ◽  
Functional Blocks ◽  
Timing Simulation ◽  
On Chip ◽  
Bus Architecture

The Advance Micro controller Bus Architecture bus protocol is used to build high performance SoC designs (system on chip). This achieves communication through the connection of different functional blocks ( or IP ). By using multiple controllers and peripherals, it makes possible to develop multiprocessor unit. It provides reusability of IP of different buses of AMBA, which can reduce the communication gap between high performance buses and low speed buses. To perform high-speed pipelined data transfers, AMBA based embedded system becomes a demanding hypothesis analytical wise, by using different bus signals supported by AMBA. To synthesize as well as simulate the composite annexation which connects advance high performance bus and advance peripheral bus which known as AHB2APB Bridge in addition to no data loss during transfer is the main target of this work. Implementation of bridge module is designed in Verilog HDL and functional and timing simulation of bridge module are done on a platform of Xilinx.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals Hardware-Assisted Security Monitoring Unit for Real-Time Ensuring Secure Instruction Execution and Data Processing in Embedded Systems

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1450
Author(s):  
Xiang Wang ◽  
Zhun Zhang ◽  
Qiang Hao ◽  
Dongdong Xu ◽  
Jiqing Wang ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Data Processing ◽  
Embedded System ◽  
High Performance ◽  
Program Execution ◽  
Security Monitoring ◽  
Railway Systems ◽  
On Chip ◽  
Capability Evaluation ◽  
Security Capability

The hardware security of embedded systems is raising more and more concerns in numerous safety-critical applications, such as in the automotive, aerospace, avionic, and railway systems. Embedded systems are gaining popularity in these safety-sensitive sectors with high performance, low power, and great reliability, which are ideal control platforms for executing instruction operation and data processing. However, modern embedded systems are still exposing many potential hardware vulnerabilities to malicious attacks, including software-level and hardware-level attacks; these can cause program execution failure and confidential data leakage. For this reason, this paper presents a novel embedded system by integrating a hardware-assisted security monitoring unit (SMU), for achieving a reinforced system-on-chip (SoC) on ensuring program execution and data processing security. This architecture design was implemented and evaluated on a Xilinx Virtex-5 FPGA development board. Based on the evaluation of the SMU hardware implementation in terms of performance overhead, security capability, and resource consumption, the experimental results indicate that the SMU does not lead to a significant speed degradation to processor while executing different benchmarks, and its average performance overhead reduces to 2.18% on typical 8-KB I/D-Caches. Security capability evaluation confirms the monitoring effectiveness of SMU against both instruction and data tampering attacks. Meanwhile, the SoC satisfies a good balance between high-security and resource overhead.

scholarly journals Adaptivity in high-performance embedded systems: a reactive control model for reliable and flexible design

2014 ◽  
Vol 29 (4) ◽  
pp. 433-451
Author(s):  
Huafeng Yu ◽  
Abdoulaye Gamatié ◽  
Éric Rutten ◽  
Jean-Luc Dekeyser
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Code Generation ◽  
High Performance ◽  
Control Model ◽  
Multimedia System ◽  
Reactive Control ◽  
Data Intensive ◽  
On Chip ◽  
Automatic Code

AbstractSystem adaptivity is increasingly demanded in high-performance embedded systems, particularly in multimedia system-on-chip (SoC), owing to growing quality-of-service requirements. This paper presents a reactive control model that has been introduced in Gaspard, our framework dedicated to SoC hardware/software co-design. This model aims at expressing adaptivity as well as reconfigurability in systems performing data-intensive computations. It is generic enough to be used for description in the different parts of an embedded system, for example, specification of how different data-intensive algorithms can be chosen according to some computation modes at the functional level; and expression of how hardware components can be selected via the usage of a library of intellectual properties according to execution performances. The transformation of this model toward synchronous languages is also presented, in order to allow an automatic code generation usable for formal verification, based on techniques such as model checking and controller synthesis, as illustrated in the paper. This work, based on Model-Driven Engineering and the standard UML MARTE profile, has been implemented in Gaspard.

CMOS INTEGRATED CIRCUIT CONTROLLERS FOR SWITCHING POWER CONVERTERS

2004 ◽  
Vol 13 (04) ◽  
pp. 789-811
Author(s):  
EDUARD ALARCÓN ◽  
GERARD VILLAR ◽  
ALBERTO POVEDA
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
High Performance ◽  
Power Converters ◽  
Correct Operation ◽  
Case Examples ◽  
Cmos Integrated Circuit ◽  
Switching Power ◽  
Switching Power Converters ◽  
On Chip

Two case examples of high-speed CMOS microelectronic implementations of high-performance controllers for switching power converters are presented. The design and implementation of a current-programmed controller and a general-purpose feedforward one-cycle controller are described. The integrated circuit controllers attain high-performance by means of using current-mode analog signal processing, hence allowing high switching frequencies that extend the operation margin compared to previous designs. Global layout-extracted transistor-level simulation results for 0.8 μm and 0.35 μm standard CMOS technologies confirm both the correct operation of the circuits in terms of bandwidth as well as their functionality for the control of switching power converters. The circuits may be used either as standalone IC controllers or as controller circuits that are technology-compatible with on-chip switching power converters and on-chip loads for future powered systems-on-chip.

scholarly journals Ultra-high speed reconfigurable microwave and radio frequency photonic intensity differentiators using Kerr frequency optical microcombs

2021 ◽  
Author(s):  
David Moss
Keyword(s):  
Radio Frequency ◽  
High Speed ◽  
High Performance ◽  
Third Order ◽  
Transversal Filter ◽  
Multi Wavelength ◽  
Gaussian Input ◽  
On Chip ◽  
The Cost ◽  
Good Agreement

Abstract We propose and experimentally demonstrate a microwave photonic intensity differentiator based on a Kerr optical comb generated by a compact integrated micro-ring resonator (MRR). The on-chip Kerr optical comb, containing a large number of comb lines, serves as a high-performance multi-wavelength source for the transversal filter, which will greatly reduce the cost, size, and complexity of the system. Moreover, owing to the compactness of the integrated MRR, up to 200-GHz frequency spacing of the Kerr optical comb can be achieved, enabling a potential operation bandwidth of over 100 GHz. By programming and shaping individual comb lines according to the calculated tap weights, a reconfigurable intensity differentiator with variable differentiation orders can be realized. The operation principle is theoretically analyzed, and experimental demonstrations of first-order, second-order, and third-order differentiation functions based on the principle are presented. The radio frequency (RF) amplitude and phase responses of multi-order intensity differentiations are characterized, and system demonstrations of real-time differentiations for Gaussian input signal are also performed. The experimental results show good agreement with theory, confirming the effectiveness of our approach.

Design and implementation of system-on-chip for peripheral component interconnect express encryption card based on multiple algorithms

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Chen Kuilin ◽  
Feng Xi ◽  
Fu Yingchun ◽  
Liu Liang ◽  
Feng Wennan ◽  
...  
Keyword(s):  
Parallel Processing ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Data Encryption ◽  
System On Chip ◽  
Content Type ◽  
Data Encryption Standard ◽  
Peripheral Component Interconnect ◽  
On Chip

Purpose The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost. Design/methodology/approach This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture. Findings This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications. Practical implications The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption. Social implications It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce. Originality/value Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

scholarly journals Dynamic Task Distribution Model for On-Chip Reconfigurable High Speed Computing System

2015 ◽  
Vol 2015 ◽  
pp. 1-12
Author(s):  
Mahendra Vucha ◽  
Arvind Rajawat
Keyword(s):  
High Speed ◽  
High Performance ◽  
Real Life ◽  
Computing System ◽  
Distribution Model ◽  
Design Parameters ◽  
Dynamic Task ◽  
Task Distribution ◽  
Field Programmable ◽  
On Chip

Modern embedded systems are being modeled as Reconfigurable High Speed Computing System (RHSCS) where Reconfigurable Hardware, that is, Field Programmable Gate Array (FPGA), and softcore processors configured on FPGA act as computing elements. As system complexity increases, efficient task distribution methodologies are essential to obtain high performance. A dynamic task distribution methodology based on Minimum Laxity First (MLF) policy (DTD-MLF) distributes the tasks of an application dynamically onto RHSCS and utilizes available RHSCS resources effectively. The DTD-MLF methodology takes the advantage of runtime design parameters of an application represented as DAG and considers the attributes of tasks in DAG and computing resources to distribute the tasks of an application onto RHSCS. In this paper, we have described the DTD-MLF model and verified its effectiveness by distributing some of real life benchmark applications onto RHSCS configured on Virtex-5 FPGA device. Some benchmark applications are represented as DAG and are distributed to the resources of RHSCS based on DTD-MLF model. The performance of the MLF based dynamic task distribution methodology is compared with static task distribution methodology. The comparison shows that the dynamic task distribution model with MLF criteria outperforms the static task distribution techniques in terms of schedule length and effective utilization of available RHSCS resources.

Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator

2016 ◽  
Author(s):  
A. J. Gines ◽  
E. Peralias ◽  
G. Leger ◽  
A. Rueda ◽  
G. Renaud ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
On Chip ◽  
Linearity Test
Sign in / Sign up

Export Citation Format

Share Document