scholarly journals Transport Triggered Array Processor for Vision Applications: Near-threshold Performance Loss Compensation Through Inherent Parallelism of Vision Array Processors

2021 ◽  
Author(s):  
Mehdi Safarpour
Keyword(s):  
Energy Efficiency ◽  
Low Voltage ◽  
Local Binary Patterns ◽  
Threshold Region ◽  
Efficient Computation ◽  
Clock Frequency ◽  
Low Level ◽  
Performance Loss ◽  
Binary Descriptors ◽  
Near Threshold

<div>Operating at reduced voltages promises substantial energy efficiency improvement, however the downside is significant down-scaling of clock frequency. This paper propose vision chips as excellent fit for low-voltage operation. Low-level sensory data processing in many Internet-of-Things (IoT) devices pursue energy efficiency by utilizing sleep modes or slowing the clocking to the minimum. To curb the share of stand-by power dissipation in those designs, near-threshold/sub-threshold operational points or ultra-low-leakage processes in fabrication are employed. Those limit the clocking rates significantly, reducing the computing throughputs of individual processing cores. In this contribution we explore compensating for the performance loss of operating in near-threshold region ($V_{dd}=$0.6V) through massive parallelization. Benefits of near-threshold operation and massive parallelism are optimum energy consumption per instruction operation and minimized memory round-trips, respectively. The Processing Elements (PE) of the design are based on Transport Triggered Architecture. The fine grained programmable parallel solution allows for fast and efficient computation of learnable low-level features (e.g. local binary descriptors and convolutions). Other operations, including Max-pooling have also been implemented. The programmable design achieves excellent energy efficiency for Local Binary Patterns computations. </div><div>Our results demonstrates that the inherent properties of chip processor and vision applications allow voltage and clock frequency aggressively without having to compromise performance. </div>

scholarly journals Transport Triggered Array Processor for Vision Applications: Near-threshold Performance Loss Compensation Through Inherent Parallelism of Vision Array Processors

2021 ◽  
Author(s):  
Mehdi Safarpour
Keyword(s):  
Energy Efficiency ◽  
Low Voltage ◽  
Local Binary Patterns ◽  
Threshold Region ◽  
Efficient Computation ◽  
Clock Frequency ◽  
Low Level ◽  
Performance Loss ◽  
Binary Descriptors ◽  
Near Threshold

<div>Operating at reduced voltages promises substantial energy efficiency improvement, however the downside is significant down-scaling of clock frequency. This paper propose vision chips as excellent fit for low-voltage operation. Low-level sensory data processing in many Internet-of-Things (IoT) devices pursue energy efficiency by utilizing sleep modes or slowing the clocking to the minimum. To curb the share of stand-by power dissipation in those designs, near-threshold/sub-threshold operational points or ultra-low-leakage processes in fabrication are employed. Those limit the clocking rates significantly, reducing the computing throughputs of individual processing cores. In this contribution we explore compensating for the performance loss of operating in near-threshold region ($V_{dd}=$0.6V) through massive parallelization. Benefits of near-threshold operation and massive parallelism are optimum energy consumption per instruction operation and minimized memory round-trips, respectively. The Processing Elements (PE) of the design are based on Transport Triggered Architecture. The fine grained programmable parallel solution allows for fast and efficient computation of learnable low-level features (e.g. local binary descriptors and convolutions). Other operations, including Max-pooling have also been implemented. The programmable design achieves excellent energy efficiency for Local Binary Patterns computations. </div><div>Our results demonstrates that the inherent properties of chip processor and vision applications allow voltage and clock frequency aggressively without having to compromise performance. </div>

An Ultra Low Voltage Low Power Self Biased Latched Comparator with Wide Input Common Mode Range for Biomedical Applications

2015 ◽  
Vol 24 (09) ◽  
pp. 1550134 ◽  
Author(s):  
Seied Zaniar Hoseini ◽  
Johar Abdekhoda ◽  
Kye-Shin Lee
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Average Power ◽  
Threshold Region ◽  
Clock Frequency ◽  
Common Mode ◽  
Common Mode Voltage ◽  
Sensing Applications ◽  
Average Power Consumption

This work describes an ultra low voltage, low power and self biased comparator with wide input common-mode range. The proposed comparator consists of a preamplifier followed by a regenerative back-to-back inverter latch, where two push pull NMOS and PMOS pairs are exploited to bias the preamplifier and adjust its output common mode voltage. This leads to a wide input common mode voltage range (from 0 V to 390 mV). Furthermore, the operation of proposed structure is relatively insensitive to process and temperature variations due to the push pull transistors, and low power consumption is achieved through sub-threshold region operation. The comparator circuit is designed using 65-nm CMOS technology with minimum supply voltage of 0.4 V. Simulation results show an average power consumption ranging from 141 nW to 188 nW for different input common mode voltage levels, where a simple power gating technique is employed to further reduce the power consumption. The Monte Carlo simulation shows an average offset of 450 μV with standard deviation of 3.3 mV. In addition, the comparator shows a kickback noise range of 0.3–2.4 mV (with input common mode range from 0 V to 390 mV) and input referred noise of 0.9 mV. The proposed comparator operates up to clock frequency of 1 MHz in most process corners and temperature range of 0–100°C which is suitable for most of the biomedical sensing applications.

scholarly journals Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1156
Author(s):  
Lorenzo Benvenuti ◽  
Alessandro Catania ◽  
Giuseppe Manfredini ◽  
Andrea Ria ◽  
Massimo Piotto ◽  
...  
Keyword(s):  
Low Voltage ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Clock Frequency ◽  
Design Environment ◽  
Ultra Low Power ◽  
Analog Cmos ◽  
Gain Error ◽  
Dc Gain

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

scholarly journals Design of an Ultra-Low Voltage Bias Current Generator Highly Immune to Electromagnetic Interference

2021 ◽  
Vol 11 (1) ◽  
pp. 6
Author(s):  
Orazio Aiello
Keyword(s):  
Integrated Circuits ◽  
Electromagnetic Interference ◽  
Low Voltage ◽  
Current Source ◽  
Building Blocks ◽  
Cmos Technology ◽  
Threshold Region ◽  
Output Current ◽  
Current Generator ◽  
Technology Process

The paper deals with the immunity to Electromagnetic Interference (EMI) of the current source for Ultra-Low-Voltage Integrated Circuits (ICs). Based on the properties of IC building blocks, such as the current-splitter and current correlator, a novel current generator is conceived. The proposed solution is suitable to provide currents to ICs operating in the sub-threshold region even in the presence of an electromagnetic polluted environment. The immunity to EMI of the proposed solution is compared with that of a conventional current mirror and evaluated by analytic means and with reference to the 180 nm CMOS technology process. The analysis highlights how the proposed solution generates currents down to nano-ampere intrinsically robust to the Radio Frequency (RF) interference affecting the input of the current generator, differently to what happens to the output current of a conventional mirror under the same conditions.

scholarly journals ENERGY EFFICIENCY IN RESIDENTIAL BUILDINGS, LESS STRAIGHT FORWARD THEN PRESUMED

2018 ◽  
Vol 13 (1) ◽  
Author(s):  
Hugo Hens
Keyword(s):  
Energy Efficiency ◽  
Energy Efficient ◽  
Energy Use ◽  
Low Voltage ◽  
Residential Buildings ◽  
Primary Energy ◽  
Heating And Cooling ◽  
Net Zero ◽  
Energy Conserving ◽  
New Construction

Since the 1990s, the successive EU directives and related national or regional legislations require new construction and retrofits to be as much as possible energy-efficient. Several measures that should stepwise minimize the primary energy use for heating and cooling have become mandated as requirement. However, in reality, related predicted savings are not seen in practice. Two effects are responsible for that. The first one refers to dweller habits, which are more energy-conserving than the calculation tools presume. In fact, while in non-energy-efficient ones, habits on average result in up to a 50% lower end energy use for heating than predicted. That percentage drops to zero or it even turns negative in extremely energy-efficient residences. The second effect refers to problems with low-voltage distribution grids not designed to transport the peaks in electricity whensunny in summer. Through that, a part of converters has to be uncoupled now and then, which means less renewable electricity. This is illustrated by examples that in theory should be net-zero buildings due to the measures applied and the presence of enough photovoltaic cells (PV) on each roof. We can conclude that mandating extreme energy efficiency far beyond the present total optimum value for residential buildings looks questionable as a policy. However, despite that, governments and administrations still seem to require even more extreme measurements regarding energy efficiency.

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