Power Efficient and Improved Noise Margin of Sram Cell for System on Chip Applications

2018 ◽  
Author(s):  
Sunil Kumar Ojha ◽  
O.P. Singh ◽  
G.R. Mishra ◽  
P.R. Vaya
Keyword(s):  
Major Part ◽  
System On Chip ◽  
Process Technology ◽  
Power Efficient ◽  
Technology Node ◽  
Noise Margin ◽  
Sram Cell ◽  
On Chip ◽  
Margin Analysis

Noise margin analysis of SRAM cell is became more crucial for on chip applications. Currently the technology is migrating towards less than 10nm node and hence it is necessary to measure the noise margin of SRAM cell very effectively, since memory is one of the major part of system on chips (SOCs) and Network on chips (NOCs) devices. If the margin is not calculated efficiently then it may leads to bad chip product and the whole device which contains this chip may not work as per the expectation. This further leads to low yield which increases the number of defective chips compared to good one. In this paper the noise margin analysis of SRAM cell is performed using 7nm process technology node using HSPICE simulator.

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

Genetic-Algorithm-based Test Pattern Generation for Crosstalk Faults between On-Chip Aggressor and Victim

2015 ◽  
Vol 25 (03) ◽  
pp. 1640018
Author(s):  
Kishore Duganapalli ◽  
Ajoy K. Palit ◽  
Walter Anheier
Keyword(s):  
Supply Voltage ◽  
Fitness Function ◽  
Vlsi Design ◽  
Pattern Generation ◽  
Test Automation ◽  
Process Technology ◽  
Noise Margin ◽  
Aspect Ratios ◽  
On Chip ◽  
Test Vectors

With the shrinking feature size and increasing aspect ratios of interconnects in DSM chips, the coupling noise between adjacent interconnects has become a major signal integrity (SI) issue, giving rise to crosstalk failures. In older technologies, SI issues have been ignored because of high noise immunity of the CMOS circuits and the process technology. However, as CMOS technologies lower down the supply voltage as well as the threshold voltage of a transistor, digital designs are more and more susceptible to noise because of the reduction of noise margin. The genetic algorithms (GAs) have been applied earlier in different engineering disciplines as potentially good optimization tools and for various applications in VLSI design, layout, EDIF digital system testing and also for test automation, particularly for stuck-at-faults and crosstalk-induced delay faults. In this paper, an elitist GA has been developed that can be used as an ATPG tool for generating the test patterns for crosstalk-induced faults between on-chip aggressor and victim and as well as for stuck-at-faults. It has been observed that the elitist GA, when the fitness function is properly defined, has immense potential in extracting the suitable test vectors quickly from randomly generated initial patterns.

scholarly journals ENERGY AND POWER EFFICIENT SYSTEM ON CHIP WITH NANOSHEET FET

2019 ◽  
Vol 01 (01) ◽  
pp. 51-59 ◽  
Author(s):  
Mohan Kumar N.
Keyword(s):  
Power Dissipation ◽  
Cost Efficiency ◽  
Power Efficiency ◽  
System On Chip ◽  
Noise Tolerance ◽  
Single Chip ◽  
Efficient System ◽  
Power Efficient ◽  
On Chip ◽  
The Cost

As the level of integration of IC increases, System on Chip (SoC) design has evolved. This technology comprises of several intellectual property blocks on a single chip. With downsizing of transistors, the traditional elements used impose several challenges such as power dissipation, leakage and so on. These factors risk the cost efficiency of microsystems and risk the semiconductor industry’s capability to prolong Moore’s law in the nanometer range. This is overcome by the introduction of carbon materials such as nanosheet FET. They are advantageous over the traditional elements in terms of area and power efficiency. We design an energy and power efficient SoC with nanosheet FET that provides noise tolerance and memory optimization.

scholarly journals SRAM CELL 6T AND 8T PARAMETRIC STABILITY ANALYSIS

2021 ◽  
Vol I (I) ◽  
Author(s):  
Bharathabau K
Keyword(s):  
Stability Analysis ◽  
High Speed ◽  
Memory Cell ◽  
Parametric Stability ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Sram Cell ◽  
Margin Analysis ◽  
Static Noise ◽  
Technology Advances

As technology advances, the need for SRAM cells that may be utilised in high-speed applications grows. SRAM cells' static noise margin (SNM) is one of the most important variables to consider when designing a memory cell, and it is the main predictor of SRAM cell speed. The static noise margin will have an impact on the read and write margins. When it comes to the SRAM Cell's stability, the SNM is very important. For high-speed SRAMs, read/write margin analysis is critical since it affects how much data can be read and written. The simulation was run using Mentor Graphics' IC Station, which utilised 350nm technology rather than 180nm technology.

Effect of Threshold Roll-Off on Static Noise Margin of Sram Cell

2018 ◽  
Author(s):  
Sunil Kumar Ojha ◽  
O.P. Singh ◽  
G.R. Mishra ◽  
P.R. Vaya
Keyword(s):  
Circuit Design ◽  
Threshold Voltage ◽  
Channel Length ◽  
Small Scale ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Sram Cell ◽  
Channel Reduction ◽  
On Chip ◽  
Static Noise

Thethreshold roll-off is a vital phenomena to be considered for any low-power and small-scale circuit design. With the advancement of the fabrication processes the channel length of the transistors is reducing rapidly, this reduction in the channel length affects the threshold voltage of the transistors very severely. To evaluate the effect of channel reduction on the threshold voltage this paper analyzes the threshold roll-off by taking SRAM cell into consideration. The reason behind choosing SRAM cell is that now the IC’s are fabricated using system on chip (SOC) design technique and currently approximately 70-80% of the SOC area are covered by memories only. One of the most important Figure of Merit for SRAM cell is its Static Noise Margin (SNM) and hence the effect of threshold-roll is implemented with respect to SNM of the SRAM cell.

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