Design and Simulation of a Pipeline Analog-to-Digital Converter

2012 ◽  
Vol 182-183 ◽  
pp. 1154-1158
Author(s):  
Guo Ping Chen ◽  
Xian Zhong Jian ◽  
Er Liang Xiao
Keyword(s):  
Sampling Frequency ◽  
System Model ◽  
Low Power Consumption ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Pipeline Adc ◽  
Analog To Digital ◽  
Simulation Results ◽  
Set Up ◽  
Accuracy Speed

The pipeline Analog-to-Digital Converter is highlight for its high resolution, accuracy, speed and low power consumption. In this paper, we have completed the design and simulation of a pipeline ADC with the SIMULINK toolbox of MATLAB. The model of 1.5 bit per stage was set up, and nine stages were connected to establish the system model. The system model can work correctly at 100MHz sampling frequency and reach 10 bit resolution. The simulation results can verify the correction of the pipeline ADC theory.

scholarly journals An Optical Analog-to-Digital Converter with Enhanced ENOB Based on MMI-Based Phase-Shift Quantization

Photonics ◽  
2021 ◽  
Vol 8 (2) ◽  
pp. 52
Author(s):  
Yue Liu ◽  
Jifang Qiu ◽  
Chang Liu ◽  
Yan He ◽  
Ran Tao ◽  
...  
Keyword(s):  
Phase Shift ◽  
Multimode Interference ◽  
Analog To Digital Converter ◽  
Effective Number ◽  
Digital Converter ◽  
Analog To Digital ◽  
Mmi Coupler ◽  
Simulation Results ◽  
Optical Analog ◽  
Optical Quantization

An optical analog-to-digital converter (OADC) scheme with enhanced bit resolution by using a multimode interference (MMI) coupler as optical quantization is proposed. The mathematical simulation model was established to verify the feasibility and to investigate the robustness of the scheme. Simulation results show that 20 quantization levels (corresponding to 4.32 of effective number of bits (ENOB)) are realized by using only 6 channels, which indicates that the scheme requires much fewer quantization channels or modulators to realize the same amount of ENOB. The scheme is robust and potential for integration.

scholarly journals Odd/Even Order Sampling Soft-Core Architecture towards Mixed Signals Fourth Industrial Revolution (4IR) Applications

Energies ◽  
2019 ◽  
Vol 12 (23) ◽  
pp. 4567
Author(s):  
Mfana ◽  
Hasan ◽  
Ali
Keyword(s):  
Industrial Revolution ◽  
Dynamic Range ◽  
Sampling Frequency ◽  
Sampling Techniques ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Fourth Industrial Revolution ◽  
Even Order

Digitization is at the center of fourth industrial revolution (4IR) with previously analog systems being digitized through an analog-to-digital converter. In addition, 4IR applications such as fifth generation (5G) Cellular Networks Technology and Cognitive Electronic Warfare (EW) at some point interface digitally through an analog-to-digital converter. Efficient use of digital resources such as memory, largely depends on the signal sampling design of analog-to-digital converters. Existing even order sampling has been found to perform better than traditional sampling techniques. Research on the efficiency of a digital interface with a 4IR platform is still in its infancy. This paper presents a performance study of three sampling techniques: the proposed new and novel odd/even order sampling architecture, existing Mod-∆, and traditional 1st order delta-sigma, to address this. Step-size signal-to-noise (SNR), dynamic range, and sampling frequency are also studied. It was found that the proposed new and novel odd/even order sampling achieved an SNR performance of 6 dB in comparison to 18 dB for Mod-∆. Sampling frequency findings indicated that the proposed new and novel odd/even order sampling achieved a sampling frequency of 2 kHz in comparison to 8 kHz from a traditional 1st order sigma-delta. Dynamic range findings indicated that the proposed odd/even order sampling has achieved a dynamic range of 1.088 volts/ms in comparison to 1.185 volts/ms from a traditional 1st order sigma-delta. Findings have indicated that the proposed odd/even order sampling has superior SNR and sampling frequency performances, while the dynamic range is reduced by 8%.

100 MS/s, 10-BIT ADC USING PIPELINED SUCCESSIVE APPROXIMATION

2014 ◽  
Vol 23 (05) ◽  
pp. 1450057
Author(s):  
SAHAR SARAFI ◽  
KHEYROLLAH HADIDI ◽  
EBRAHIM ABBASPOUR ◽  
ABU KHARI BIN AAIN ◽  
JAVAD ABBASZADEH
Keyword(s):  
Successive Approximation ◽  
Sar Adc ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Process Technology ◽  
Total Conversion ◽  
Analog To Digital ◽  
Simulation Results

This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined SAR-ADC's speed. The proposed method reduces the total conversion without limiting the ADC performance. To evaluate the proposed method a 10-bit 100 MS/s is designed in 0.5 μm CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 9-MHz input with 54.19 dB SNDR while consuming 57.3 mw from a 5-V supply.

Digitally Assisted Backend Correction Pipeline ADC Verilog-A Modeling

2012 ◽  
Vol 457-458 ◽  
pp. 1122-1128
Author(s):  
Yue Hong Gong ◽  
Min Luo ◽  
Jian Guo Ma
Keyword(s):  
Power Consumption ◽  
Open Loop ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Pipeline Adc ◽  
Traditional Use ◽  
Analog To Digital ◽  
Second Stage ◽  
Nonlinear Error ◽  
System Power

In this paper, a 12 bits pipeline ADC (analog to digital converter) based on digitally assisted backend correction is described and behaviorally modeled in Verilog-A language. The Verilog-A model is simulated with Cadence Spectre simulator. In the traditional use of pipeline ADC, the for-end sample and hold amplifier occupies the most power consumption. To decreases the system power consumption, open-loop amplifier is used in the first residual amplify circuit between first and second stage sub-ADC. To correct the nonlinear error introduced by the open-loop amplifier, backend digitally correction is applied.

scholarly journals An Embedded Low Transistor Count 8-bit Analog-to-digital Converter Using a Binary Searching Method

VLSI Design ◽  
2002 ◽  
Vol 14 (2) ◽  
pp. 193-202
Author(s):  
Chua-Chin Wang ◽  
Ya-Hsin Hsueh ◽  
Shao-Ku Huang
Keyword(s):  
Binary Search ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Simulation Results ◽  
On Chip ◽  
Searching Method ◽  
Cost Issue ◽  
The Cost ◽  
System Designs

Small analog-to-digital converter (ADCs) are very popular when they are required in many interfaces or system designs. Ever since the system-on-chip (SOC) became one of the major trends in chip designs, the demand for small and less power draining ADCs has urgently emerged. The area factor is particularly critical when it comes to the cost issue. In this paper, a small but stable ADC intellectual property (IP) macro design is proposed wherein a binary search scheme is utilized to produce the ADC function. A total of eight cycles are needed to convert the analog signal based upon simulation results. A physical chip is fabricated to verify the correctness of our design.

scholarly journals Design of A 5-Bit Fully Parallel Analog to Digital Converter Using Common Gate Differrential Mos Pair-Based Comparator

2015 ◽  
Vol 66 (5) ◽  
pp. 250-256 ◽  
Author(s):  
Oktay Aytar
Keyword(s):  
Cmos Technology ◽  
Sampling Frequency ◽  
State University ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
North Carolina State University ◽  
Programmable Logic Array ◽  
Common Gate ◽  
Logic Array

Abstract This paper presents a novel comparator structure based on the common gate differential MOS pair. The proposed comparator has been applied to fully parallel analog to digital converter (A/D converter). Furthermore, this article presents 5 bit fully parallel A/D Converter design using the cadence IC5141 design platform and NCSU(North Carolina State University) design kit with 0.18 μm CMOS technology library. The proposed fully parallel A/D converter consist of resistor array block, comparator block, 1-n decoder block and programmable logic array. The 1-n decoder block includes latch block and thermometer code circuit that is implemented using transmission gate based multiplexer circuit. Thus, sampling frequency and analog bandwidth are increased. The INL and DNL of the proposed fully parallel A/D converter are (0/ + 0.63) LSB and (−0.26/ + 0.31) LSB at a sampling frequency of 5 GS/s with an input signal of 50 MHz, respectively. The proposed fully parallel A/D Converter consumes 340 mW from 1.8 V supply.

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